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Searched refs:DT_REG_ADDR_BY_IDX (Results 1 – 25 of 49) sorted by relevance

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/Zephyr-latest/soc/intel/intel_socfpga/agilex5/
Dmmu_regions.c23 DT_REG_ADDR_BY_IDX(DT_NODELABEL(pinmux), 0),
28 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
33 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/arm/qemu_cortex_a53/
Dmmu_regions.c14 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/arm/qemu_virt_arm64/
Dmmu_regions.c14 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/brcm/bcm2711/
Dmmu_regions.c12 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
17 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/brcm/bcm2712/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/arm/fvp_aemv8a/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/xen/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/rockchip/rk3399/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/ti/k3/am6x/a53/
Dmmu_regions.c14 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
19 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/renesas/rcar/rcar_gen3/
Dmmu_regions.c12 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
17 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/renesas/rcar/rcar_gen4/a55/
Dmmu_regions.c12 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
17 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/rockchip/rk35/rk3568/
Dmmu_regions.c15 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
20 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/rockchip/rk35/rk3588s/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/nxp/layerscape/ls1046a/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-latest/soc/nxp/imx/imx9/imx95/a55/
Dmmu_regions.c13 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
17 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Difx_cat1-pinctrl.h103 (DT_REG_ADDR_BY_IDX(DT_GPIO_CTLR_BY_IDX(node, gpios_prop, 0), 0) - \
104 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 0)) / \
105 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 1), \
/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c23 struct pcr_regs *pcr = ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0)); in pcr_clock_regs()
42 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_clock_regs()
70 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_power_fail()
115 struct pcr_regs *pcr = ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0)); in pcr_clock_regs()
161 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_clock_regs()
169 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_power_fail()
/Zephyr-latest/soc/intel/intel_socfpga/agilex/
Dmmu_regions.c30 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
35 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/nxp/imx/imx9/imx91/
Dmmu_regions.c12 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
16 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dlinker.ld18 …FLEXSPI1 (wx) : ORIGIN = DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi1), 1), LENGTH = DT_REG_SIZE_BY_I…
21 …FLEXSPI2 (wx) : ORIGIN = DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi2), 1), LENGTH = DT_REG_SIZE_BY_I…
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dmmu_regions.c14 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
19 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.c89 #define ECLIC_CFG (*((volatile union CLICCFG *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 0))))
90 #define ECLIC_INFO (*((volatile union CLICINFO *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 1))))
91 #define ECLIC_MTH (*((volatile union CLICMTH *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 2))))
92 #define ECLIC_CTRL ((volatile struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3)))
/Zephyr-latest/soc/nxp/imx/imx9/imx93/a55/
Dmmu_regions.c13 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
17 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/samples/application_development/code_relocation_nocopy/
Dlinker_arm_nocopy.ld34 #define EXTFLASH_SIZE DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_ospi_nor), 1)
41 #define EXTFLASH_SIZE DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_qspi_nor), 1)
48 #define EXTFLASH_SIZE DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_xspi_nor), 1)
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dgic.h23 #define GIC_DIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0)
24 #define GIC_CPU_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)

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