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Searched refs:DT_INST_CLOCKS_CELL_BY_IDX (Results 1 – 17 of 17) sorted by relevance

/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h326 #define DT_INST_CLOCKS_CELL_BY_IDX(inst, idx, cell) \ macro
348 DT_INST_CLOCKS_CELL_BY_IDX(inst, 0, cell)
/Zephyr-latest/drivers/pwm/
Dpwm_rcar.c258 .mod_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
259 .mod_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
260 .core_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
261 .core_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
Dpwm_renesas_ra.c555 .mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(index, 0, mstp), \
556 .stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(index, 0, stop_bit), \
/Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/
Deth_nxp_enet_qos.c36 .clock_subsys = (void *)DT_INST_CLOCKS_CELL_BY_IDX(n, 0, name), \
/Zephyr-latest/drivers/video/
Dvideo_mcux_mipi_csi2rx.c342 .clock_root = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(n, 0, name), \
343 .clock_ui = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(n, 1, name), \
344 .clock_esc = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(n, 2, name), \
/Zephyr-latest/drivers/adc/
Dadc_mcux_adc16.c448 .trg_offset = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, offset), \
449 .trg_bits = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, bits), \
450 .alt_offset = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, offset), \
451 .alt_bits = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, bits),
/Zephyr-latest/drivers/rtc/
Drtc_ll_stm32.c118 #if DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_HSE
360 #if DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_HSE in rtc_stm32_init()
1067 #if DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_HSE
1087 #if DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSI
1091 #elif DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSE
1095 #elif DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_HSE
/Zephyr-latest/drivers/gpio/
Dgpio_rcar.c302 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
304 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
/Zephyr-latest/drivers/serial/
Duart_rcar.c548 .mod_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
549 .mod_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
550 .bus_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
551 .bus_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
/Zephyr-latest/drivers/i2c/
Di2c_rcar.c364 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
366 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
/Zephyr-latest/drivers/display/
Ddisplay_renesas_ra.c426 .clock_glcdc_subsys = {.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, mstp), \
427 .stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(id, 0, stop_bit)}, \
/Zephyr-latest/drivers/ptp_clock/
Dptp_clock_nxp_enet.c255 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, name), \
/Zephyr-latest/drivers/can/
Dcan_rcar.c1196 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
1198 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
1200 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
1202 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
/Zephyr-latest/drivers/sdhc/
Drcar_mmc.c2196 .cpg_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
2197 .cpg_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
2198 .bus_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
2199 .bus_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
/Zephyr-latest/drivers/counter/
Dcounter_ll_stm32_rtc.c65 #if DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSI
/Zephyr-latest/drivers/i2s/
Di2s_mcux_sai.c1189 (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name), \
/Zephyr-latest/tests/lib/devicetree/api/src/
Dmain.c2298 zassert_equal(DT_INST_CLOCKS_CELL_BY_IDX(0, 2, bits), 2, ""); in ZTEST()
2299 zassert_equal(DT_INST_CLOCKS_CELL_BY_IDX(0, 2, bus), 8, ""); in ZTEST()