Searched refs:CFGR1_REG (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32c0_clock.h | 39 #define CFGR1_REG 0x08 macro
51 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
52 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
53 #define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 16, CFGR1_REG)
54 #define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 20, CFGR1_REG)
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| D | stm32f0_clock.h | 34 #define CFGR1_REG 0x04 macro
52 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
53 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
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| D | stm32f1_clock.h | 32 #define CFGR1_REG 0x04 macro
46 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
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| D | stm32wba_clock.h | 75 #define CFGR1_REG 0x1C macro
77 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
78 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
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| D | stm32h5_clock.h | 65 #define CFGR1_REG 0x1C macro
126 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 22, CFGR1_REG)
127 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 18, CFGR1_REG)
128 #define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR1_REG)
129 #define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR1_REG)
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| D | stm32f10x_clock.h | 22 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
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| D | stm32u5_clock.h | 64 #define CFGR1_REG 0x1C macro
111 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
112 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
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| D | stm32n6_clock.h | 160 #define CFGR1_REG 0x20 macro
163 #define CPU_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR1_REG)
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