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Searched refs:CACHE_IA_INTR_SOURCE (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h35 #define CACHE_IA_INTR_SOURCE 25 macro
Desp-esp32c3-intmux.h46 #define CACHE_IA_INTR_SOURCE 36 macro
Desp-xtensa-intmux.h79 #define CACHE_IA_INTR_SOURCE 68 /* Cache Invalid Access, LEVEL */ macro
Desp32s3-xtensa-intmux.h62 #define CACHE_IA_INTR_SOURCE 56 /* interrupt of Cache Invalid Access, LEVEL*/ macro
Desp32s2-xtensa-intmux.h80 #define CACHE_IA_INTR_SOURCE 70 /* Cache Invalid Access, level */ macro