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/Zephyr-latest/drivers/flash/
Dflash_stm32wbx.c5 * SPDX-License-Identifier: Apache-2.0
39 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
40 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
44 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
45 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
46 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
49 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
50 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
55 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
56 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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/Zephyr-latest/doc/hardware/peripherals/edac/
Dibecc.rst12 The In-Band Error Correction Code (IBECC) improves reliability by providing
15 not support the out-of-band ECC.
18 and used to store ECC syndrome data. IBECC converts read / write transactions
23 IBECC functionality. ECC errors are injected on the write path and cause ECC
32 * OPERATION_MODE = 0x0 sets functional mode to protect requests based on
38 * OPERATION_MODE = 0x2 sets functional mode to protect all requests and ignore
58 * Correctable Error (CE) - error is detected and corrected by IBECC module.
60 * Uncorrectable Error (UE) - error is detected by IBECC module and not
63 The IBECC driver provides error type for the higher-level application to
65 syndrome is not used in the IBECC driver but provided to higher-level
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/Zephyr-latest/dts/bindings/mtd/
Datmel,at2x-base.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: eeprom-base.yaml
15 address-width:
22 description: EEPROM write cycle timeout in milliseconds
23 wp-gpios:
24 type: phandle-array
26 GPIO to which the write-protect pin of the chip is connected.
28 The device will interpret this signal as active-low.
Dfujitsu,mb85rcxx.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: ["eeprom-base.yaml", i2c-device.yaml]
21 address-width:
26 wp-gpios:
27 type: phandle-array
28 description: GPIO to which the write-protect pin of the chip is connected.
Djedec,spi-nor-common.yaml3 # SPDX-License-Identifier: Apache-2.0
5 # Common properties used by nodes describing M25P80-compatible SPI NOR
8 # This extends JESD216-defined features with additional functionality
9 # that may be specific to the vendor of a M25P80-compatible device and
17 requires-ulbpr:
23 protection register that initializes to write-protected. Use this
24 property to indicate that the BPR must be unlocked before write
27 has-dpd:
33 Power-Down mode that is entered by command 0xB9 to reduce power
37 Electronic Signature; see t-enter-dpd).
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/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_pins.h4 * SPDX-License-Identifier: Apache-2.0
19 * @brief NPCX pin-mux configuration structure
22 * pin-muxing and its polarity to enable alternative functionality.
32 * @brief NPCX low-voltage configuration structure
35 * low-voltage detection.
38 uint8_t ctrl:5; /** Related register index for low-voltage conf. */
39 uint8_t bit:3; /** Related register bit for low-voltage conf. */
51 * @brief Force the internal SPI flash write-protect pin (WP) to low level to
52 * protect the flash Status registers.
57 * @brief Get write protection status
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/Zephyr-latest/doc/kernel/usermode/
Doverview.rst15 Example use-cases of Zephyr's user mode features:
17 - The kernel can protect against many unintentional programming errors which
20 - The kernel can sandbox complex data parsers such as interpreters, network
21 protocols, and filesystems such that malicious third-party code or data
24 - The kernel can support the notion of multiple logical "applications", each
31 For threads running in a non-privileged CPU state (hereafter referred to as
32 'user mode') we aim to protect against the following:
34 - We prevent access to memory not specifically granted, or incorrect access to
35 memory that has an incompatible policy, such as attempting to write to a
36 read-only area.
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/Zephyr-latest/soc/renesas/rzt2m/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
19 /* Safety area protect register */
25 /* Non-safety area protect register */
54 /* PRC Key Code - this value is required to allow any write operation
/Zephyr-latest/dts/bindings/sdhc/
Drenesas,ra-sdhc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-sdhc"
9 include: [sdhc.yaml, pinctrl-device.yaml]
16 bus-width:
19 - 1
20 - 4
23 sd-support:
26 mmc-support:
29 card-detect:
32 write-protect:
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/Zephyr-latest/soc/st/stm32/common/
Dstm32_hsem.h4 * SPDX-License-Identifier: Apache-2.0
18 * Index of the semaphore used by CPU2 to prevent the CPU1 to either write or
19 * erase data in flash. The CPU1 shall not either write or erase in flash when
20 * this semaphore is taken by the CPU2. When the CPU1 needs to either write or
24 * CPU2 is using PES bit. By default, CPU2 is using the PES bit to protect its
31 * Index of the semaphore used by CPU1 to prevent the CPU2 to either write or
32 * erase data in flash. In order to protect its timing, the CPU1 may get this
33 * semaphore to prevent the CPU2 to either write or erase in flash
123 retry--; in z_stm32_hsem_lock()
141 return -EAGAIN; in z_stm32_hsem_try_lock()
/Zephyr-latest/samples/drivers/spi_fujitsu_fram/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
78 return -EIO; in mb85rs64v_read_id()
82 return -EIO; in mb85rs64v_read_id()
86 return -EIO; in mb85rs64v_read_id()
90 return -EIO; in mb85rs64v_read_id()
94 return -EIO; in mb85rs64v_read_id()
105 /* disable write protect */ in write_bytes()
109 printk("unable to disable write protect\n"); in write_bytes()
110 return -EIO; in write_bytes()
113 /* write cmd */ in write_bytes()
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/Zephyr-latest/drivers/clock_control/
Dclock_control_renesas_cpg_mssr.h2 * Copyright (c) 2022-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
46 #define RCAR_CPG_NONE -1
82 /* CPG write protect offset */
102 /* CPG write protect offset */
/Zephyr-latest/boards/shields/x_nucleo_eeprma2/doc/
Dindex.rst3 X-NUCLEO-EEPRMA2 EEPROM memory expansion board
9 The ST X-NUCLEO-EEPRMA2 expansion board can be used to evaluate M24xx series I2C
11 The X-NUCLEO-EEPRMA2 expansion board is compatible with the Arduino UNO R3
20 :alt: X-NUCLEO-EEPRMA2
23 `X-NUCLEO-EEPRMA2 website`_.
32 The SPI EEPROM devices can write protect complete memory blocks by setting
33 the corresponding block protect bits in the status register.
38 and the X-NUCLEO-EEPRMA2 in particular, see these ST Microelectronics documents:
40 - `X-NUCLEO-EEPRMA2 EEPROM memory expansion board User Manual`_
42 - `M24C02-F Serial I2C bus EEPROM Datasheet`_
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/Zephyr-latest/include/zephyr/drivers/
Dflash.h2 * Copyright (c) 2017-2024 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
60 /** Minimal write alignment and size */
69 * write or does not require it at all.
80 /** Set for ordinary Flash where erase is needed before write of random data */
85 #define FLASH_ERASE_CAPS_UNSET (int)-1
110 return (p->caps.no_explicit_erase) ? 0 : FLASH_ERASE_C_EXPLICIT; in flash_params_get_erase_cap()
132 * @brief Flash write implementation handler type
134 * @note Any necessary write protection management must be performed by
135 * the driver, with the driver responsible for ensuring the "write-protect"
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/Zephyr-latest/tests/drivers/flash/stm32/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
36 flash_get_page_info_by_offs(dev, offset + size - 1, &end_page)) { in sector_mask_from_offset()
37 return -EINVAL; in sector_mask_from_offset()
40 *mask = ((1UL << (end_page.index + 1)) - 1) & in sector_mask_from_offset()
41 ~((1UL << start_page.index) - 1); in sector_mask_from_offset()
73 /* Check if region is not write protected. */ in flash_stm32_setup()
76 zassert_equal(rc, 0, "Cannot get write protect status"); in flash_stm32_setup()
82 TC_PRINT("Removing write protection\n"); in flash_stm32_setup()
88 zassert_equal(rc, 0, "Cannot remove write protection"); in flash_stm32_setup()
97 if (buf[i] != flash_params->erase_value) { in flash_stm32_setup()
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/Zephyr-latest/doc/services/storage/nvs/
Dnvs.rst3 Non-Volatile Storage (NVS)
6 Elements, represented as id-data pairs, are stored in flash using a
7 FIFO-managed circular buffer. The flash area is divided into sectors. Elements
10 sector it is checked that identifier - data pairs exist in the sectors in use,
11 if not the id-data pair is copied.
13 The id is a 16-bit unsigned number. NVS ensures that for each used id there is
14 at least one id-data pair stored in flash at all time.
23 only calculated over the metadata and only ensures that a write has been
25 CRC-32. Use the :kconfig:option:`CONFIG_NVS_DATA_CRC` configuration item to enable
35 A write of data to nvs always starts with writing the data, followed by a write
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/Zephyr-latest/dts/bindings/mspi/
Dmspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: mspi
14 mspi-max-frequency:
22 mspi-io-mode:
25 - "MSPI_IO_MODE_SINGLE"
26 - "MSPI_IO_MODE_DUAL"
27 - "MSPI_IO_MODE_DUAL_1_1_2"
28 - "MSPI_IO_MODE_DUAL_1_2_2"
29 - "MSPI_IO_MODE_QUAD"
30 - "MSPI_IO_MODE_QUAD_1_1_4"
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/Zephyr-latest/soc/espressif/common/
DKconfig.flash2 # SPDX-License-Identifier: Apache-2.0
36 modules, please don't disable this, otherwise your flash may not work in 4-bit
81 This option should be enabled, if any one of the following is true: (1) need to write
82 to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main
115 bool "Protect unmapped memory regions from unintended accesses"
/Zephyr-latest/drivers/eeprom/
Deeprom_mb85rsxx.c4 * SPDX-License-Identifier: Apache-2.0
24 #define EEPROM_MB85RSXX_WREN 0x06U /* Set Write Enable Latch */
25 #define EEPROM_MB85RSXX_WRDI 0x04U /* Reset Write Enable Latch */
27 #define EEPROM_MB85RSXX_WRSR 0x01U /* Write Status Register */
29 #define EEPROM_MB85RSXX_WRITE 0x02U /* Write Memory Code */
35 #define EEPROM_MB85RSXX_STATUS_WPEN BIT(7) /* Status Register Write Protect (RW) */
38 #define EEPROM_MB85RSXX_STATUS_WEL BIT(1) /* Write Enable Latch (RO) */
64 const struct eeprom_mb85rsxx_config *config = dev->config; in eeprom_mb85rsxx_read()
65 struct eeprom_mb85rsxx_data *data = dev->data; in eeprom_mb85rsxx_read()
70 if (offset + len > config->size) { in eeprom_mb85rsxx_read()
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/Zephyr-latest/include/zephyr/ipc/
Dpbuf.h4 * SPDX-License-Identifier: Apache-2.0
59 * Used for validation - TODO: To be
88 * buffer with read/write semantics on top of a memory region shared
93 * is encapsulated to a message (with length header). The read/write API is
94 * written in a way to protect the data from being corrupted.
100 struct pbuf_data data; /* Data used to read and write
122 .len = (uint32_t)((uint32_t)(size) - MAX(dcache_align, _PBUF_IDX_SIZE) - \
130 * It contains the read index, write index and padding.
172 * @retval -EINVAL when the input parameter is incorrect.
188 * @retval -EINVAL when the input parameter is incorrect.
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/Zephyr-latest/arch/xtensa/core/
DCMakeLists.txt1 # SPDX-License-Identifier: Apache-2.0
3 zephyr_cc_option(-mlongcalls)
45 # -dM, supported by all Xtensa toolchains) core-isa.h file available
46 # as "core-isa-dM.h". This can be easily parsed by non-C tooling.
49 # are the official places where we find core-isa.h. (Also that we
51 # to build this file to protect against mismatched versions.)
52 set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM.h)
53 set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
54 file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
56 COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ ${XTENSA_CORE_LOCAL_C_FLAG}
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_arcv2_irq_unit.c3 * Copyright (c) 2020-2022 Synopsys.
5 * SPDX-License-Identifier: Apache-2.0
14 * The interrupt unit is optional in the ARCv2-based processors. When
31 * - select round-robbin in arc_shared_intc_init()
32 * - disable all lines in arc_shared_intc_init()
40 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) { in arc_shared_intc_init()
52 * Fake round-robin: we allow to distribute interrupts only to primary core as in arc_shared_intc_init()
70 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) { in arc_shared_intc_update_post_smp()
86 #define ARC_IRQ_DEFAULT_PRIORITY ((CONFIG_NUM_IRQ_PRIO_LEVELS - 1) | _ARC_V2_IRQ_PRIORITY_SECURE)
88 #define ARC_IRQ_DEFAULT_PRIORITY (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
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/Zephyr-latest/samples/subsys/usb/mass/
DREADME.rst1 .. zephyr:code-sample:: usb-mass
3 :relevant-api: usbd_api usbd_msc_device _usb_device_core_api file_system_api
25 The selection between a RAM-based or a FLASH-based disk and file system
26 can be chosen passing Kconfig configuration via the -D command-line switch.
28 RAM-disk Example without any file system
31 The default configurations selects RAM-based disk without any file system.
32 This example only needs additional 96KiB RAM for the RAM-disk and is intended
35 .. zephyr-app-commands::
36 :zephyr-app: samples/subsys/usb/mass
38 :gen-args: -DEXTRA_DTC_OVERLAY_FILE="ramdisk.overlay"
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/Zephyr-latest/drivers/sdhc/
Drcar_mmc_registers.h4 * SPDX-License-Identifier: Apache-2.0
18 #define RCAR_MMC_CMD_RD BIT(12) /* 1: read, 0: write */
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
55 * detect/write protect state.
72 #define RCAR_MMC_INFO2_CLEAR BIT(11) /* the write value should always be 1 */
73 #define RCAR_MMC_INFO2_BWE BIT(9) /* write buffer ready */
78 #define RCAR_MMC_INFO2_ERR_ILW BIT(4) /* illegal write err */
146 /* SD Buffer Read/Write Register */
/Zephyr-latest/boards/shields/x_nucleo_eeprma2/
Dx_nucleo_eeprma2.overlay4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
40 address-width = <16>;
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