Lines Matching +full:write +full:- +full:protect
3 * Copyright (c) 2020-2022 Synopsys.
5 * SPDX-License-Identifier: Apache-2.0
14 * The interrupt unit is optional in the ARCv2-based processors. When
31 * - select round-robbin in arc_shared_intc_init()
32 * - disable all lines in arc_shared_intc_init()
40 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) { in arc_shared_intc_init()
52 * Fake round-robin: we allow to distribute interrupts only to primary core as in arc_shared_intc_init()
70 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) { in arc_shared_intc_update_post_smp()
86 #define ARC_IRQ_DEFAULT_PRIORITY ((CONFIG_NUM_IRQ_PRIO_LEVELS - 1) | _ARC_V2_IRQ_PRIORITY_SECURE)
88 #define ARC_IRQ_DEFAULT_PRIORITY (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
105 * no need to protect the window between a write to IRQ_SELECT and subsequent writes to the
117 * System with IDU case (most likely multi-core system): in arc_core_private_intc_init()
118 * - disable private IRQs: they will be enabled with irq_enable before usage in arc_core_private_intc_init()
119 * - enable shared (IDU) IRQs: their enabling / disabling is controlled via IDU, so we in arc_core_private_intc_init()
121 * System without IDU case (single-core system): in arc_core_private_intc_init()
122 * - disable all IRQs: they will be enabled with irq_enable before usage in arc_core_private_intc_init()
146 * We initialize per-core part for core 0 here, in arc_irq_init()