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Searched +full:write +full:- +full:inactive +full:- +full:cycles (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/dts/bindings/mipi-dbi/
Dnxp,lcdic.yaml2 # SPDX-License-Identifier: Apache-2.0
5 NXP LCDIC Controller. This controller implements 8080 and SPI mode MIPI-DBI
9 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
21 nxp,swap-bytes:
27 reset-gpios:
28 type: phandle-array
34 nxp,write-inactive-cycles:
38 Set minimum count of write inactive cycles, as a multiple of the module
39 clock frequency. This controls the length of the inactive period of the
42 nxp,write-active-cycles:
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/Zephyr-latest/boards/shields/lcd_par_s035/boards/
Drd_rw612_bga.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
11 * - Depopulate resistors R78, R604, R598, R15, R245, R243, R11, R20, R237,
13 * - Populate resistors R286, R19, R246, R242, R123, R239, R124, R125, R236,
15 * - Remove jumper JP30
16 * - Set jumper JP40 to postion 1-2, JP38 to 1-2, and JP16 to position 2-3
21 * ON-ON-OFF (8 bit 8080 mode), and connect the following pins
23 * |-----------|-------------|----------|
62 slew-rate = "ultra";
67 mipi-mode = "MIPI_DBI_MODE_8080_BUS_8_BIT";
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/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
56 Min. time, in nanoseconds, the #CS line should remain inactive between
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/Zephyr-latest/drivers/watchdog/
Dwdt_dw.h1 /* SPDX-License-Identifier: Apache-2.0 */
19 * and programmed based on user-defined options.
66 #define RPL_PCLK_CYCLES2 0x0 /* 2 pclk cycles */
67 #define RPL_PCLK_CYCLES4 0x1 /* 4 pclk cycles */
68 #define RPL_PCLK_CYCLES8 0x2 /* 8 pclk cycles */
69 #define RPL_PCLK_CYCLES16 0x3 /* 16 pclk cycles */
70 #define RPL_PCLK_CYCLES32 0x4 /* 32 pclk cycles */
71 #define RPL_PCLK_CYCLES64 0x5 /* 64 pclk cycles */
72 #define RPL_PCLK_CYCLES128 0x6 /* 128 pclk cycles */
73 #define RPL_PCLK_CYCLES256 0x7 /* 256 pclk cycles */
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/Zephyr-latest/drivers/pwm/
Dpwm_mcux.c4 * SPDX-License-Identifier: Apache-2.0
46 const struct pwm_mcux_config *config = dev->config; in mcux_pwm_set_cycles_internal()
47 struct pwm_mcux_data *data = dev->data; in mcux_pwm_set_cycles_internal()
56 if (period_cycles != data->period_cycles[channel] in mcux_pwm_set_cycles_internal()
57 || level != data->channel[channel].level) { in mcux_pwm_set_cycles_internal()
61 data->period_cycles[channel] = period_cycles; in mcux_pwm_set_cycles_internal()
63 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_set_cycles_internal()
65 return -EINVAL; in mcux_pwm_set_cycles_internal()
68 data->channel[channel].pwmchannelenable = true; in mcux_pwm_set_cycles_internal()
70 PWM_StopTimer(config->base, 1U << config->index); in mcux_pwm_set_cycles_internal()
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/Zephyr-latest/drivers/flash/
Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
36 * * Some devices support a Deep Power-Down mode which reduces current
41 * * PM_DEVICE_STATE_SUSPENDED corresponds to deep-power-down mode;
63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
66 /* MXICY Low-power/high perf mode is second bit in configuration register 2 */
72 /* Build-time data associated with the device. */
92 /* Expected JEDEC ID, from jedec-id property */
96 /* Optional support for entering 32-bit address mode. */
101 /* Length of BFP structure, in 32-bit words. */
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/Zephyr-latest/drivers/spi/
Dspi_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
47 /* Bi-directional mode */
106 cfg->regs->SPI_CTRL_REG |= SPI_SPI_CTRL_REG_SPI_ON_Msk; in spi_smartbond_enable()
107 cfg->regs->SPI_CTRL_REG &= ~SPI_SPI_CTRL_REG_SPI_RST_Msk; in spi_smartbond_enable()
109 cfg->regs->SPI_CTRL_REG &= ~SPI_SPI_CTRL_REG_SPI_ON_Msk; in spi_smartbond_enable()
110 cfg->regs->SPI_CTRL_REG |= SPI_SPI_CTRL_REG_SPI_RST_Msk; in spi_smartbond_enable()
116 return (!!(cfg->regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_ON_Msk)) && in spi_smartbond_isenabled()
117 (!(cfg->regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_RST_Msk)); in spi_smartbond_isenabled()
122 const struct spi_smartbond_cfg *cfg = dev->config; in spi_smartbond_write_word()
123 struct spi_smartbond_data *data = dev->data; in spi_smartbond_write_word()
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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/Zephyr-latest/include/zephyr/
Dkernel.h4 * SPDX-License-Identifier: Apache-2.0
53 #define K_PRIO_COOP(x) (-(CONFIG_NUM_COOP_PRIORITIES - (x)))
56 #define K_HIGHEST_THREAD_PRIO (-CONFIG_NUM_COOP_PRIORITIES)
60 #define K_LOWEST_APPLICATION_THREAD_PRIO (K_LOWEST_THREAD_PRIO - 1)
245 * bits, arch-specific use high bits.
289 * from within a user-provided callback they have been invoked.
290 * Effectively it serves as a tiny bit of zero-overhead TLS data.
328 /* end - thread options */
335 * - @ref K_USER allocate a userspace thread (requires `CONFIG_USERSPACE=y`)
353 * @retval -EBUSY if the thread stack is in use.
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