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/Zephyr-latest/dts/bindings/mm/
Dintel,adsp-tlb.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,adsp-tlb"
15 paddr-size:
20 exec-bit-idx:
22 description: Index of the execute permission bit.
24 write-bit-idx:
26 description: Index of the write permission bit.
Dintel,adsp-mtl-tlb.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,adsp-mtl-tlb"
15 paddr-size:
20 exec-bit-idx:
22 description: Index of the execute permission bit.
24 write-bit-idx:
26 description: Index of the write permission bit.
/Zephyr-latest/include/zephyr/drivers/misc/coresight/
Dstmesp.h4 * SPDX-License-Identifier: Apache-2.0
62 return &reg->G_DMTS[0]; in _stmesp_get_data_reg()
64 return &reg->G_DTS[0]; in _stmesp_get_data_reg()
68 return &reg->I_DMTS[0]; in _stmesp_get_data_reg()
70 return &reg->I_DTS[0]; in _stmesp_get_data_reg()
76 return &reg->G_DM[0]; in _stmesp_get_data_reg()
78 return &reg->G_D[0]; in _stmesp_get_data_reg()
82 return &reg->I_DM[0]; in _stmesp_get_data_reg()
84 return &reg->I_D[0]; in _stmesp_get_data_reg()
92 /** @brief Write flag to STMESP
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/Zephyr-latest/drivers/pinctrl/
Dpinctrl_mchp_mec5.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
23 * in the control register. Hardware sets output state bit in both control and
25 * register bit is writable by the EC. We also clear the input pad disable
26 * bit because we need the input pin state and we don't know if the requested
27 * alternate function is input or bi-directional.
36 size_t idx = 0; in mec5_config_pin() local
41 return -EINVAL; in mec5_config_pin()
46 return -EIO; in mec5_config_pin()
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Dpinctrl_mchp_xec.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
16 * Microchip XEC: each GPIO pin has two 32-bit control register.
17 * The first 32-bit register contains all pin features except
24 static void config_drive_slew(struct gpio_regs * const regs, uint32_t idx, uint32_t conf) in config_drive_slew() argument
41 val |= ((drvstr - 1u) << MCHP_GPIO_CTRL2_DRV_STR_POS); in config_drive_slew()
48 regs->CTRL2[idx] = (regs->CTRL2[idx] & ~msk) | (val & msk); in config_drive_slew()
53 * None, weak pull-up, weak pull-down, or repeater mode (both pulls enabled).
55 * If the no-bias boolean is set then disable internal pulls.
61 if (conf & BIT(MCHP_XEC_NO_PUD_POS)) { in prog_pud()
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3.c5 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
35 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
39 #define LPI_PROPBASE_SZ(nrbits) ROUND_UP(BIT(nrbits), KB(64))
40 #define LPI_PENDBASE_SZ(nrbits) ROUND_UP(BIT(nrbits) / 8, KB(64))
50 return gic_rdists[arch_curr_cpu()->id]; in gic_get_rdist()
54 * Wait for register write pending
64 rwp_mask = BIT(GICR_CTLR_RWP); in gic_wait_rwp()
67 rwp_mask = BIT(GICD_CTLR_RWP); in gic_wait_rwp()
80 uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192]; in arm_gic_lpi_setup()
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Dintc_mchp_ecia_xec.c4 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
72 ((const struct xec_ecia_config *const)(ecia_dev)->config)
75 ((const struct xec_girq_config *const)(girq_dev)->config)
78 ((struct xec_girq_src_data *const)(girq_dev)->data)
82 * bit-wise or of all the GIRQ's result bits.
89 regs->BLK_EN_SET = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
91 regs->BLK_EN_CLR = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
103 /* write 1 to clear */ in mchp_xec_ecia_girq_src_clr()
104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()
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/Zephyr-latest/subsys/net/lib/lwm2m/
Dlwm2m_obj_access_control.c4 * SPDX-License-Identifier: Apache-2.0
19 #define READ BIT(0)
20 #define WRITE BIT(1) macro
21 #define ACEXEC BIT(2)
22 #define DELETE BIT(3)
23 #define CREATE BIT(4)
26 #define WRITE_ATTR BIT(8)
27 #define DISCOVER BIT(9)
36 return WRITE; in operation_to_acperm()
92 * + ACCESS_CONTROL_MAX_ID - 1 (not counting the acl instance)
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/Zephyr-latest/include/zephyr/logging/
Dlog_frontend_stmesp.h4 * SPDX-License-Identifier: Apache-2.0
21 * Log frontend optionally dumps buffered data and start to write to the STM
27 * @retval -EIO if there was an internal failure.
38 /** @brief Perform a dummy write to STMESP.
46 * Write a trace point information using STM. Number of unique trace points is limited
47 * to 32768 - CONFIG_LOG_FRONTEND_STMESP_TP_CHAN_BASE per core.
65 /** @brief Trace point with 32 bit data.
67 * Write a trace point information using STM. Number of unique trace points is limited
68 * to 32768 - CONFIG_LOG_FRONTEND_STMESP_TP_CHAN_BASE per core.
71 * @param d Data. 32 bit word.
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/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps_bank.c6 * SPDX-License-Identifier: Apache-2.0
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
34 * - Pull up
35 * - Pull down
36 * - Open drain
37 * - Open source.
45 * -EINVAL if the specified pin index is out of range,
46 * -ENOTSUP if the pin configuration data contains a flag
55 uint32_t pin_mask = BIT(pin); in gpio_xlnx_ps_pin_configure()
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Dgpio_pcal64xxa.c5 * SPDX-License-Identifier: Apache-2.0
131 struct pcal64xxa_drv_data *drv_data = dev->data; in pcal64xxa_pin_configure()
132 const struct pcal64xxa_drv_cfg *drv_cfg = dev->config; in pcal64xxa_pin_configure()
137 LOG_DBG("%s: configure pin %i with flags 0x%08X", dev->name, pin, flags); in pcal64xxa_pin_configure()
139 /* This device does not support open-source outputs, and open-drain in pcal64xxa_pin_configure()
140 * outputs can be only configured port-wise. in pcal64xxa_pin_configure()
143 return -ENOTSUP; in pcal64xxa_pin_configure()
151 return -ENOTSUP; in pcal64xxa_pin_configure()
155 return -EWOULDBLOCK; in pcal64xxa_pin_configure()
158 k_sem_take(&drv_data->lock, K_FOREVER); in pcal64xxa_pin_configure()
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/Zephyr-latest/drivers/flash/
Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
36 * * Some devices support a Deep Power-Down mode which reduces current
41 * * PM_DEVICE_STATE_SUSPENDED corresponds to deep-power-down mode;
63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
66 /* MXICY Low-power/high perf mode is second bit in configuration register 2 */
72 /* Build-time data associated with the device. */
92 /* Expected JEDEC ID, from jedec-id property */
96 /* Optional support for entering 32-bit address mode. */
101 /* Length of BFP structure, in 32-bit words. */
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/Zephyr-latest/include/zephyr/drivers/pcie/
Dcontroller.h10 * SPDX-License-Identifier: Apache-2.0
34 * @brief Function called to read a 32-bit word from an endpoint's configuration space.
36 * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
48 * @brief Function called to write a 32-bit word to an endpoint's configuration space.
50 * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
56 * @param data the value to write
73 * @param mem64 True if the BAR is of 64bit memory type
75 * @param bar_bus_addr bus-centric address allocated to be written in the BAR register
92 * @param mem64 True if the BAR is of 64bit memory type
94 * @param bar_base_addr bus-centric address allocation base
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/Zephyr-latest/drivers/i3c/
Di3c_npcx.c4 * SPDX-License-Identifier: Apache-2.0
103 #define I3C_BUS_TLOW_PP_MIN_NS 24 /* T_LOW period in push-pull mode */
104 #define I3C_BUS_THigh_PP_MIN_NS 24 /* T_High period in push-pull mode */
105 #define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */
107 #define PPBAUD_DIV_MAX (BIT(GET_FIELD_SZ(NPCX_I3C_MCONFIG_PPBAUD)) - 1) /* PPBAUD divider max */
121 (BIT(NPCX_I3C_MSTATUS_MCTRLDONE) | BIT(NPCX_I3C_MSTATUS_COMPLETE) | \
122 BIT(NPCX_I3C_MSTATUS_IBIWON) | BIT(NPCX_I3C_MSTATUS_NOWCNTLR))
125 (BIT(NPCX_I3C_INTSET_START) | BIT(NPCX_I3C_INTSET_MATCHED) | BIT(NPCX_I3C_INTSET_STOP) | \
126 BIT(NPCX_I3C_INTSET_DACHG) | BIT(NPCX_I3C_INTSET_CCC) | BIT(NPCX_I3C_INTSET_ERRWARN) | \
127 BIT(NPCX_I3C_INTSET_HDRMATCH) | BIT(NPCX_I3C_INTSET_CHANDLED) | \
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Di3c_mcux.c6 * SPDX-License-Identifier: Apache-2.0
125 * @brief Read a register and test for bit matches with timeout.
129 * @param reg Pointer to 32-bit Register.
135 * @retval -ETIMEDOUT Timedout without matching.
143 * quickly (some sub-microseconds) so no extra in reg32_poll_timeout()
147 return -ETIMEDOUT; in reg32_poll_timeout()
155 * @param reg Pointer to 32-bit Register.
173 * @param reg Pointer to 32-bit register.
190 * @param reg Pointer to 32-bit register.
209 uint32_t intmask = base->MINTSET; in mcux_i3c_interrupt_disable()
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/Zephyr-latest/drivers/led_strip/
Dws2812_i2s.c5 * https://electronut.in/nrf52-i2s-ws2812/
7 * Note: the word "word" refers to a 32-bit integer unless otherwise stated.
11 * The I2S peripheral sends two 16-bit channel values for each clock period.
12 * A single LED color (8 data bits) will take up one 32-bit word or one LRCK
15 * SPDX-License-Identifier: Apache-2.0
28 #include <zephyr/dt-bindings/led/led.h>
49 /* Serialize an 8-bit color channel value into two 16-bit I2S values (or 1 32-bit
68 const struct ws2812_i2s_cfg *cfg = dev->config; in ws2812_strip_update_rgb()
69 const uint8_t sym_one = cfg->nibble_one; in ws2812_strip_update_rgb()
70 const uint8_t sym_zero = cfg->nibble_zero; in ws2812_strip_update_rgb()
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/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
27 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
52 uint8_t gpr_shift: 5; /* bitshift for GPR register write */
55 uint8_t gpr_val: 1; /* value to write to GPR register */
60 uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
81 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
82 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
84 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
86 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
/Zephyr-latest/arch/xtensa/core/
Dgdbstub.c4 * SPDX-License-Identifier: Apache-2.0
118 * which is 0-255. in read_sreg()
120 regno = reg->regno & 0xFF; in read_sreg()
125 * hard-coded at compile time. in read_sreg()
323 reg->val = val; in read_sreg()
324 reg->seqno = ctx->seqno; in read_sreg()
428 int idx, num_laddr_regs; in copy_to_ctx() local
432 if ((int *)bsa - stack > 4) { in copy_to_ctx()
434 } else if ((int *)bsa - stack > 8) { in copy_to_ctx()
436 } else if ((int *)bsa - stack > 12) { in copy_to_ctx()
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/Zephyr-latest/soc/nxp/imx/imx9/imx93/
Dpinctrl_soc.h2 * Copyright (c) 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
24 #define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
47 uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
62 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
63 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
65 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
67 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
24 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
49 uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
64 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
65 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
67 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
69 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
24 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
49 uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
64 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
65 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
67 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
69 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
24 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
49 uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
64 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
65 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
67 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
69 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
24 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
49 uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
64 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
65 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
67 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
69 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
/Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
24 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
48 uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
63 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
64 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
66 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
68 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
29 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
98 uint8_t gpr_shift: 5; /* bitshift for GPR register write */
101 uint8_t gpr_val: 1; /* value to write to GPR register */
110 uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
135 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ argument
136 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
138 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ argument
140 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
141 IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \
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