Lines Matching +full:write +full:- +full:bit +full:- +full:idx
6 * SPDX-License-Identifier: Apache-2.0
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
34 * - Pull up
35 * - Pull down
36 * - Open drain
37 * - Open source.
45 * -EINVAL if the specified pin index is out of range,
46 * -ENOTSUP if the pin configuration data contains a flag
55 uint32_t pin_mask = BIT(pin); in gpio_xlnx_ps_pin_configure()
64 return -ENOTSUP; in gpio_xlnx_ps_pin_configure()
79 * The output enable bit can be set after the initial in gpio_xlnx_ps_pin_configure()
88 * -> Write the initial output value into the data register. in gpio_xlnx_ps_pin_configure()
98 /* Set the pin's output enable bit */ in gpio_xlnx_ps_pin_configure()
105 * Disable the output first in case of an O -> I in gpio_xlnx_ps_pin_configure()
116 * @brief Reads the current bit mask of the entire GPIO pin bank.
118 * Reads the current bit mask of the entire bank from the
119 * read-only data register. This includes the current values
125 * to which the current bit mask read from the bank's
129 * -EINVAL if the pointer to the output variable is NULL.
142 * @brief Masked write of a bit mask for the entire GPIO pin bank.
144 * Performs a masked write operation on the data register of
182 * as a read-modify-write operation. All bits set in the bit
188 * @param pins Bit mask specifying which bits shall be set in
211 * as a read-modify-write operation. All bits set in the bit
217 * @param pins Bit mask specifying which bits shall be cleared
240 * as a read-modify-write operation. All bits set in the bit
246 * @param pins Bit mask specifying which bits shall be toggled
273 * - edge or level triggered,
274 * - rising edge / high level or falling edge / low level,
275 * - in edge mode only: trigger on both rising and falling edge.
285 * -EINVAL if the specified pin index is out of range,
286 * -ENOTSUP if the interrupt configuration data contains an
296 uint32_t pin_mask = BIT(pin); in gpio_xlnx_ps_bank_pin_irq_configure()
303 /* Disable the specified pin's interrupt before (re-)configuring it */ in gpio_xlnx_ps_bank_pin_irq_configure()
317 return -EINVAL; in gpio_xlnx_ps_bank_pin_irq_configure()
328 return -EINVAL; in gpio_xlnx_ps_bank_pin_irq_configure()
344 /* Clear potential stale pending bit before enabling interrupt */ in gpio_xlnx_ps_bank_pin_irq_configure()
356 * form of a bit mask where each pin with a pending interrupt is
357 * indicated. This information can either be used by the PM sub-
360 * of how many bank sub-devices exist. As the current status is
366 * @retval A bit mask indicating for which pins within the bank
384 * @brief Callback management re-direction function.
386 * Re-directs any callback management calls relating to the current
387 * GPIO bank to the GPIO sub-system. Comp. documentation of the
388 * underlying sub-system's #gpio_manage_callback function.
394 * @retval A bit mask indicating for which pins within the bank
403 return gpio_manage_callback(&dev_data->callbacks, callback, set); in gpio_xlnx_ps_bank_manage_callback()
420 * @brief Initialize a MIO / EMIO GPIO bank sub-device
422 * Initialize a MIO / EMIO GPIO bank sub-device, which is a child
423 * of the parent Xilinx PS GPIO controller device driver. This ini-
436 __ASSERT(dev_data->base != 0, "%s mapped base address missing", dev->name); in gpio_xlnx_ps_bank_init()
437 if (dev_data->base == 0) { in gpio_xlnx_ps_bank_init()
438 LOG_ERR("%s mapped base address missing", dev->name); in gpio_xlnx_ps_bank_init()
439 return -EIO; in gpio_xlnx_ps_bank_init()
452 #define GPIO_XLNX_PS_BANK_INIT(idx)\ argument
453 static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {\
455 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
457 .bank_index = idx,\
459 static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = {\
462 DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL,\
463 &gpio_xlnx_ps_bank##idx##_data, &gpio_xlnx_ps_bank##idx##_cfg,\