5  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
35  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
39 #define LPI_PROPBASE_SZ(nrbits)	ROUND_UP(BIT(nrbits), KB(64))
40 #define LPI_PENDBASE_SZ(nrbits)	ROUND_UP(BIT(nrbits) / 8, KB(64))
50 	return gic_rdists[arch_curr_cpu()->id];  in gic_get_rdist()
54  * Wait for register write pending
64 		rwp_mask = BIT(GICR_CTLR_RWP);  in gic_wait_rwp()
67 		rwp_mask = BIT(GICD_CTLR_RWP);  in gic_wait_rwp()
80 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_setup()
83 		*cfg |= BIT(0);  in arm_gic_lpi_setup()
85 		*cfg &= ~BIT(0);  in arm_gic_lpi_setup()
95 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_set_priority()
107 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_is_enabled()
109 	return (*cfg & BIT(0));  in arm_gic_lpi_is_enabled()
136 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_set_priority()
137 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_set_priority()  local
143 	sys_write32(mask, ICENABLER(base, idx));  in arm_gic_irq_set_priority()
151 		idx = intid / GIC_NUM_CFG_PER_REG;  in arm_gic_irq_set_priority()
152 		shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;  in arm_gic_irq_set_priority()
154 		val = sys_read32(ICFGR(base, idx));  in arm_gic_irq_set_priority()
159 		sys_write32(val, ICFGR(base, idx));  in arm_gic_irq_set_priority()
171 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_enable()
172 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_enable()  local
176 	 * Affinity routing is enabled for Armv8-A Non-secure state (GICD_CTLR.ARE_NS  in arm_gic_irq_enable()
185 	sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_enable()
196 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_disable()
197 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_disable()  local
199 	sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_disable()
200 	/* poll to ensure write is complete */  in arm_gic_irq_disable()
211 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_is_enabled()
212 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_is_enabled()  local
215 	val = sys_read32(ISENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_is_enabled()
222 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_is_pending()
223 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_is_pending()  local
226 	val = sys_read32(ISPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_is_pending()
233 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_set_pending()
234 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_set_pending()  local
236 	sys_write32(mask, ISPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_set_pending()
241 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_clear_pending()
242 	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;  in arm_gic_irq_clear_pending()  local
244 	sys_write32(mask, ICPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_clear_pending()
251 	/* (Pending -> Active / AP) or (AP -> AP) */  in arm_gic_get_active()
261 	 * by clearing interrupt condition by a write to the peripheral  in arm_gic_eoi()
262 	 * register. It is desired that the write transfer is complete  in arm_gic_eoi()
264 	 * a new state on seeing 'EOI write'.  in arm_gic_eoi()
272 	/* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */  in arm_gic_eoi()
309 	if (!(sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))) {  in gicv3_rdist_enable()
314 		if (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) {  in gicv3_rdist_enable()
317 			while (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) {  in gicv3_rdist_enable()
324 	while (sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)) {  in gicv3_rdist_enable()
360 	      ((lpi_id_bits - 1) & GITR_PROPBASER_ID_BITS_MASK);  in gicv3_rdist_setup_lpis()
393 	/* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */  in gicv3_cpuif_init()
447 	unsigned int idx;  in gicv3_dist_init()  local
453 	 * but GIC distributor should avoid to be re-configured in order to avoid crash the  in gicv3_dist_init()
456 	if (sys_read32(GICD_CTLR) & (BIT(GICD_CTLR_ENABLE_G0) | BIT(GICD_CTLR_ENABLE_G1NS))) {  in gicv3_dist_init()
484 		idx = intid / GIC_NUM_INTR_PER_REG;  in gicv3_dist_init()
487 			    ICENABLER(base, idx));  in gicv3_dist_init()
490 			    ICPENDR(base, idx));  in gicv3_dist_init()
491 		sys_write32(IGROUPR_VAL, IGROUPR(base, idx));  in gicv3_dist_init()
493 			    IGROUPMODR(base, idx));  in gicv3_dist_init()
508 		idx = intid / GIC_NUM_CFG_PER_REG;  in gicv3_dist_init()
509 		sys_write32(0, ICFGR(base, idx));  in gicv3_dist_init()
514 	sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),  in gicv3_dist_init()
523 	 * Since the GICD_CTLR_ARE and GICD_CTRL_ARE_S share BIT(4), and  in gicv3_dist_init()
525 	 * BIT(1), we can reuse them.  in gicv3_dist_init()
527 	sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS),  in gicv3_dist_init()
605 	cpu = arch_curr_cpu()->id;  in __arm_gic_init()