2  * Copyright (c) 2016 Open-RnD Sp. z o.o.
7  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
23  * in the control register. Hardware sets output state bit in both control and
25  * register bit is writable by the EC. We also clear the input pad disable
26  * bit because we need the input pin state and we don't know if the requested
27  * alternate function is input or bi-directional.
36 	size_t idx = 0;  in mec5_config_pin()  local
41 		return -EINVAL;  in mec5_config_pin()
46 		return -EIO;  in mec5_config_pin()
52 		cfg2[idx].prop = MEC_GPIO_SLEW_RATE_ID;  in mec5_config_pin()
53 		cfg2[idx].val = (uint8_t)MEC_GPIO_SLEW_RATE_SLOW;  in mec5_config_pin()
55 			cfg2[idx].val = (uint8_t)MEC_GPIO_SLEW_RATE_FAST;  in mec5_config_pin()
57 		idx++;  in mec5_config_pin()
63 		cfg2[idx].prop = MEC_GPIO_DRV_STR_ID;  in mec5_config_pin()
64 		cfg2[idx].val = (uint8_t)(temp - 1u);  in mec5_config_pin()
65 		idx++;  in mec5_config_pin()
68 	/* Touch internal pull-up/pull-down? */  in mec5_config_pin()
69 	cfg2[idx].prop = MEC_GPIO_PUD_PROP_ID;  in mec5_config_pin()
70 	if (conf & BIT(MCHP_XEC_NO_PUD_POS)) {  in mec5_config_pin()
71 		cfg2[idx++].val = MEC_GPIO_PROP_NO_PUD;  in mec5_config_pin()
72 	} else if (conf & BIT(MCHP_XEC_PU_POS)) {  in mec5_config_pin()
73 		cfg2[idx++].val = MEC_GPIO_PROP_PULL_UP;  in mec5_config_pin()
74 	} else if (conf & BIT(MCHP_XEC_PD_POS)) {  in mec5_config_pin()
75 		cfg2[idx++].val = MEC_GPIO_PROP_PULL_DN;  in mec5_config_pin()
79 	if (conf & (BIT(MCHP_XEC_OUT_DIS_POS) | BIT(MCHP_XEC_OUT_EN_POS))) {  in mec5_config_pin()
80 		cfg2[idx].prop = MEC_GPIO_DIR_PROP_ID;  in mec5_config_pin()
81 		cfg2[idx].val = MEC_GPIO_PROP_DIR_IN;  in mec5_config_pin()
82 		if (conf & BIT(MCHP_XEC_OUT_EN_POS)) {  in mec5_config_pin()
83 			cfg2[idx].val = MEC_GPIO_PROP_DIR_OUT;  in mec5_config_pin()
85 		idx++;  in mec5_config_pin()
88 	/* Touch output state? Bit can be set even if the direction is input only */  in mec5_config_pin()
89 	if (conf & (BIT(MCHP_XEC_OUT_LO_POS) | BIT(MCHP_XEC_OUT_HI_POS))) {  in mec5_config_pin()
90 		cfg2[idx].prop = MEC_GPIO_CTRL_OUT_VAL_ID;  in mec5_config_pin()
91 		cfg2[idx].val = 0u;  in mec5_config_pin()
92 		if (conf & BIT(MCHP_XEC_OUT_HI_POS)) {  in mec5_config_pin()
93 			cfg2[idx].val = 1u;  in mec5_config_pin()
95 		idx++;  in mec5_config_pin()
99 	if (conf & (BIT(MCHP_XEC_PUSH_PULL_POS) | BIT(MCHP_XEC_OPEN_DRAIN_POS))) {  in mec5_config_pin()
100 		cfg2[idx].prop = MEC_GPIO_OBUFT_PROP_ID;  in mec5_config_pin()
101 		cfg2[idx].val = MEC_GPIO_PROP_PUSH_PULL;  in mec5_config_pin()
102 		if (conf & BIT(MCHP_XEC_OPEN_DRAIN_POS)) {  in mec5_config_pin()
103 			cfg2[idx].val = MEC_GPIO_PROP_OPEN_DRAIN;  in mec5_config_pin()
105 		idx++;  in mec5_config_pin()
109 	cfg2[idx].prop = MEC_GPIO_PWRGT_PROP_ID;  in mec5_config_pin()
110 	cfg2[idx].val = MEC_GPIO_PROP_PWRGT_VTR;  in mec5_config_pin()
111 	if (conf & BIT(MCHP_XEC_PIN_LOW_POWER_POS)) {  in mec5_config_pin()
112 		cfg2[idx].val = MEC_GPIO_PROP_PWRGT_OFF;  in mec5_config_pin()
114 	idx++;  in mec5_config_pin()
117 	cfg2[idx].prop = MEC_GPIO_MUX_PROP_ID;  in mec5_config_pin()
118 	cfg2[idx].val = (uint8_t)altf;  in mec5_config_pin()
119 	idx++;  in mec5_config_pin()
121 	/* Always touch invert of alternate function. Need another bit to avoid touching */  in mec5_config_pin()
122 	cfg2[idx].prop = MEC_GPIO_FUNC_POL_PROP_ID;  in mec5_config_pin()
123 	cfg2[idx].val = MEC_GPIO_PROP_FUNC_OUT_NON_INV;  in mec5_config_pin()
124 	if (conf & BIT(MCHP_XEC_FUNC_INV_POS)) {  in mec5_config_pin()
125 		cfg2[idx].val = MEC_GPIO_PROP_FUNC_OUT_INV;  in mec5_config_pin()
127 	idx++;  in mec5_config_pin()
130 	ret = mec_hal_gpio_set_props(pin, cfg2, idx);  in mec5_config_pin()
132 		return -EIO;  in mec5_config_pin()
135 	/* make output state in control read-only in control and read-write in parallel reg */  in mec5_config_pin()
138 		return -EIO;  in mec5_config_pin()
156 			return -EINVAL;  in pinctrl_configure_pins()