| /Zephyr-latest/dts/bindings/serial/ |
| D | infineon,xmc4xxx-uart.yaml | 3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11 input-src:
20 - "DX0A"
21 - "DX0B"
22 - "DX0C"
23 - "DX0D"
24 - "DX0E"
25 - "DX0F"
26 - "DX0G"
[all …]
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| D | zephyr,uart-emul.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,uart-emul"
8 include: uart-controller.yaml
11 tx-fifo-size:
15 Size of the virtual UART TX FIFO
17 rx-fifo-size:
21 Size of the virtual UART RX FIFO
26 Connects TX to RX internally creating a loop back connection. Useful
29 latch-buffer-size:
33 Size of the virtual UART latch buffer.
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| D | zephyr,nus-uart.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,nus-uart"
9 tx-fifo-size:
13 Size of the virtual UART TX FIFO
15 rx-fifo-size:
19 Size of the virtual UART RX FIFO
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| D | zephyr,cdc-acm-uart.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,cdc-acm-uart"
8 include: uart-controller.yaml
10 on-bus: usb
13 tx-fifo-size:
17 Size of the virtual CDC ACM UART TX FIFO
19 rx-fifo-size:
23 Size of the virtual CDC ACM UART RX FIFO
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| /Zephyr-latest/tests/drivers/uart/uart_emul/ |
| D | uart_emul.overlay | 4 * SPDX-License-Identifier: Apache-2.0
8 euart0: uart-emul {
9 compatible = "zephyr,uart-emul";
11 current-speed = <0>;
12 rx-fifo-size = <256>;
13 tx-fifo-size = <256>;
16 euart1: uart-dummy-bus {
17 compatible = "zephyr,uart-emul";
19 current-speed = <0>;
20 rx-fifo-size = <256>;
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| /Zephyr-latest/dts/bindings/spi/ |
| D | nxp,dspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
20 pcs-sck-delay:
26 sck-pcs-delay:
32 transfer-delay:
38 pinctrl-0:
41 nxp,rx-tx-chn-share:
43 description: If the edma channel shared with tx and rx
48 ctar register selection range form 0-1 for master mode, 0 for slave mode
50 sample-point:
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| D | xlnx,xps-spi-2.00.a.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "xlnx,xps-spi-2.00.a"
8 include: spi-controller.yaml
11 # https://github.com/Xilinx/device-tree-xlnx
20 xlnx,num-ss-bits:
24 - 1
25 - 2
26 - 3
27 - 4
31 xlnx,num-transfer-bits:
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| /Zephyr-latest/tests/subsys/logging/log_backend_uart/ |
| D | multi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,log-uart = &log_uarts;
13 compatible = "zephyr,log-uart";
17 euart0: uart-emul0 {
18 compatible = "zephyr,uart-emul";
20 current-speed = <0>;
21 rx-fifo-size = <256>;
22 tx-fifo-size = <256>;
25 euart1: uart-emul1 {
26 compatible = "zephyr,uart-emul";
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| D | single.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,log-uart = &log_uarts;
13 compatible = "zephyr,log-uart";
17 euart0: uart-emul0 {
18 compatible = "zephyr,uart-emul";
20 current-speed = <0>;
21 rx-fifo-size = <256>;
22 tx-fifo-size = <256>;
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| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.nxp_s32_gmac | 1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
17 int "TX ring length"
21 Length of the TX ring. ETH_NXP_S32_TX_RING_BUF_SIZE * ETH_NXP_S32_TX_RING_LEN
22 must be a multiple of TX FIFO block size.
25 int "TX ring data buffer size"
29 Size, in bytes, of the TX data buffer. The size must be big enough to
39 must be a multiple of RX FIFO block size.
42 int "RX ring data buffer size"
46 Size, in bytes, of the RX data buffer. The size must be big enough to
[all …]
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| /Zephyr-latest/tests/drivers/uart/uart_async_api/boards/ |
| D | xmc45_relax_kit.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
7 current-speed = <921600>;
8 pinctrl-0 = <&uart_tx_p5_0_u2c0 &uart_rx_p5_1_u2c0>;
9 pinctrl-names = "default";
10 input-src = "DX0G";
12 interrupt-names = "tx", "rx";
14 dma-names = "tx", "rx";
15 fifo-start-offset = <0>;
[all …]
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| D | xmc47_relax_kit.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
9 /delete-property/ scl-src;
10 /delete-property/ sda-src;
12 current-speed = <921600>;
14 interrupt-names = "tx", "rx";
16 dma-names = "tx", "rx";
17 pinctrl-0 = <&uart_tx_p3_15_u1c1 &uart_rx_p3_14_u1c1>;
18 pinctrl-names = "default";
[all …]
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| /Zephyr-latest/dts/bindings/dma/ |
| D | gd,gd32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller with FIFO
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
[all …]
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| D | st,stm32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 This DMA controller includes FIFO control registers.
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
24 -bit 9 : Peripheral Increment Address
[all …]
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| /Zephyr-latest/tests/subsys/shell/shell_backend_uart/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
8 euart0: uart-emul0 {
9 compatible = "zephyr,uart-emul";
11 current-speed = <0>;
12 rx-fifo-size = <256>;
13 tx-fifo-size = <256>;
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| /Zephyr-latest/samples/subsys/logging/logger/ |
| D | bt.overlay | 4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "zephyr,nus-uart";
14 rx-fifo-size = <1024>;
15 tx-fifo-size = <1024>;
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| /Zephyr-latest/boards/infineon/xmc47_relax_kit/ |
| D | xmc47_relax_kit.dts | 2 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include <infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include "xmc47_relax_kit-pinctrl.dtsi"
22 die-temp0 = &die_temp;
23 pwm-led0 = &pwm_led1;
29 compatible = "gpio-leds";
40 compatible = "pwm-leds";
55 zephyr,shell-uart = &usic0ch0;
[all …]
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| /Zephyr-latest/snippets/nus-console/ |
| D | nus-console.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 zephyr,shell-uart = &bt_nus_console_uart;
14 compatible = "zephyr,nus-uart";
15 rx-fifo-size = <1024>;
16 tx-fifo-size = <1024>;
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| /Zephyr-latest/samples/subsys/shell/shell_module/ |
| D | bt.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 zephyr,shell-uart = &bt_nus_console_uart;
14 compatible = "zephyr,nus-uart";
15 rx-fifo-size = <1024>;
16 tx-fifo-size = <1024>;
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| /Zephyr-latest/dts/bindings/dai/ |
| D | nxp,dai-esai.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-esai"
13 dai-index:
21 tx-fifo-watermark:
24 Use this property to specify the watermark value for the TX
25 FIFO. This value needs to be in FIFO words (NOT BYTES). This
28 the TX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
29 rx-fifo-watermark:
33 FIFO. This values needs to be in FIFO words (NOT BYTES). This
36 the RX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
[all …]
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| D | nxp,dai-sai.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-sai"
8 include: [base.yaml, pinctrl-device.yaml]
13 mclk-is-output:
21 rx-fifo-watermark:
24 Use this property to specify the watermark value for the TX
25 FIFO. This value needs to be in FIFO words (NOT BYTES). This
28 tx-fifo-watermark:
32 FIFO. This value needs to be in FIFO words (NOT BYTES). This
37 fifo-depth:
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| /Zephyr-latest/doc/services/ipc/ipc_service/backends/ |
| D | ipc_service_icmsg.rst | 27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
28 …This must be the largest value of the invalidation or the write-back size for both sides of the co…
30 * Define two memory regions and assign them to ``tx-region`` and ``rx-region``
40 Make sure that you set correct value of the ``dcache-alignment``.
46 .. code-block:: devicetree
48 reserved-memory {
49 tx: memory@20070000 {
60 compatible = "zephyr,ipc-icmsg";
61 dcache-alignment = <32>;
62 tx-region = <&tx>;
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| /Zephyr-latest/tests/drivers/uart/uart_basic_api/src/ |
| D | test_uart_fifo.c | 4 * SPDX-License-Identifier: Apache-2.0
11 * @brief TestPurpose: verify UART works well in fifo mode
13 * - Test Steps
14 * - FIFO Output:
15 * -# Set UART IRQ callback using uart_irq_callback_set().
16 * -# Enable UART TX IRQ using uart_irq_tx_enable().
17 * -# Output the prepared data using uart_fifo_fill().
18 * -# Disable UART TX IRQ using uart_irq_tx_disable().
19 * -# Compare the number of characters sent out with the
20 * original data size.
[all …]
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| /Zephyr-latest/drivers/serial/ |
| D | uart_sifive.c | 2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
20 #define RXDATA_EMPTY (1 << 31) /* Receive FIFO Empty */
23 #define TXDATA_FULL (1 << 31) /* Transmit FIFO Full */
25 #define TXCTRL_TXEN (1 << 0) /* Activate Tx Channel */
29 #define IE_TXWM (1 << 0) /* TX Interrupt Enable/Pending */
33 * RX/TX Threshold count to generate TX/RX Interrupts.
39 uint32_t tx; member
73 ((const struct uart_sifive_device_config * const)(dev)->config)->port)
78 * Writes data to tx register if transmitter is not full.
[all …]
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| /Zephyr-latest/drivers/i2s/ |
| D | i2s_litex.c | 4 * SPDX-License-Identifier: Apache-2.0
22 val = (val == max - 1) ? 0 : val + 1; \
50 * @brief Reset i2s fifo
79 return -EINVAL; in i2s_get_foramt()
158 * This function copies data from fifo into user buffer
160 * @param dst memory destination where fifo data will be copied to
161 * @param size amount of data to be copied
165 static void i2s_copy_from_fifo(uint8_t *dst, size_t size, int sample_width, in i2s_copy_from_fifo() argument
172 for (size_t i = 0; i < size / chan_size; i += 4) { in i2s_copy_from_fifo()
173 /* using sys_read function, as fifo is not a csr, in i2s_copy_from_fifo()
[all …]
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