2  * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4  * SPDX-License-Identifier: Apache-2.0
20 #define RXDATA_EMPTY   (1 << 31)   /* Receive FIFO Empty */
23 #define TXDATA_FULL    (1 << 31)   /* Transmit FIFO Full */
25 #define TXCTRL_TXEN    (1 << 0)    /* Activate Tx Channel */
29 #define IE_TXWM        (1 << 0)    /* TX Interrupt Enable/Pending */
33  * RX/TX Threshold count to generate TX/RX Interrupts.
39 	uint32_t tx;  member
73 	 ((const struct uart_sifive_device_config * const)(dev)->config)->port)
78  * Writes data to tx register if transmitter is not full.
88 	/* Wait while TX FIFO is full */  in uart_sifive_poll_out()
89 	while (uart->tx & TXDATA_FULL) {  in uart_sifive_poll_out()
92 	uart->tx = (int)c;  in uart_sifive_poll_out()
101  * @return 0 if a character arrived, -1 if the input buffer if empty.
106 	uint32_t val = uart->rx;  in uart_sifive_poll_in()
109 		return -1;  in uart_sifive_poll_in()
120  * @brief Fill FIFO with data
124  * @param size Number of bytes to send
130 				 int size)  in uart_sifive_fifo_fill()  argument
135 	for (i = 0; i < size && !(uart->tx & TXDATA_FULL); i++) {  in uart_sifive_fifo_fill()
136 		uart->tx = (int)tx_data[i];  in uart_sifive_fifo_fill()
143  * @brief Read data from FIFO
147  * @param size Container size
153 				 const int size)  in uart_sifive_fifo_read()  argument
159 	for (i = 0; i < size; i++) {  in uart_sifive_fifo_read()
160 		val = uart->rx;  in uart_sifive_fifo_read()
173  * @brief Enable TX interrupt in ie register
181 	uart->ie |= IE_TXWM;  in uart_sifive_irq_tx_enable()
185  * @brief Disable TX interrupt in ie register
193 	uart->ie &= ~IE_TXWM;  in uart_sifive_irq_tx_disable()
197  * @brief Check if Tx IRQ has been raised
207 	return !!(uart->ip & IE_TXWM);  in uart_sifive_irq_tx_ready()
222 	 * No TX EMPTY flag for this controller,  in uart_sifive_irq_tx_complete()
223 	 * just check if TX FIFO is not full  in uart_sifive_irq_tx_complete()
225 	return !(uart->tx & TXDATA_FULL);  in uart_sifive_irq_tx_complete()
237 	uart->ie |= IE_RXWM;  in uart_sifive_irq_rx_enable()
249 	uart->ie &= ~IE_RXWM;  in uart_sifive_irq_rx_disable()
263 	return !!(uart->ip & IE_RXWM);  in uart_sifive_irq_rx_ready()
288 	return !!(uart->ip & (IE_RXWM | IE_TXWM));  in uart_sifive_irq_is_pending()
306 	struct uart_sifive_data *data = dev->data;  in uart_sifive_irq_callback_set()
308 	data->callback = cb;  in uart_sifive_irq_callback_set()
309 	data->cb_data = cb_data;  in uart_sifive_irq_callback_set()
314 	struct uart_sifive_data *data = dev->data;  in uart_sifive_irq_handler()
316 	if (data->callback) {  in uart_sifive_irq_handler()
317 		data->callback(dev, data->cb_data);  in uart_sifive_irq_handler()
326 	const struct uart_sifive_device_config * const cfg = dev->config;  in uart_sifive_init()
332 	/* Enable TX and RX channels */  in uart_sifive_init()
333 	uart->txctrl = TXCTRL_TXEN | CTRL_CNT(cfg->txcnt_irq);  in uart_sifive_init()
334 	uart->rxctrl = RXCTRL_RXEN | CTRL_CNT(cfg->rxcnt_irq);  in uart_sifive_init()
337 	uart->div = cfg->sys_clk_freq / cfg->baud_rate - 1;  in uart_sifive_init()
341 	uart->ie = 0U;  in uart_sifive_init()
344 	cfg->cfg_func();  in uart_sifive_init()
348 	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);  in uart_sifive_init()