1# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
2# SPDX-License-Identifier: Apache-2.0
3
4description: Xilinx AXI Quad SPI IP node
5
6compatible: "xlnx,xps-spi-2.00.a"
7
8include: spi-controller.yaml
9
10# Property names correspond to a subset of those generated by
11# https://github.com/Xilinx/device-tree-xlnx
12
13properties:
14  reg:
15    required: true
16
17  interrupts:
18    required: true
19
20  xlnx,num-ss-bits:
21    type: int
22    required: true
23    enum:
24      - 1
25      - 2
26      - 3
27      - 4
28    description: |
29      Number of slave select bits implemented
30
31  xlnx,num-transfer-bits:
32    type: int
33    required: true
34    enum:
35      - 8
36      - 16
37      - 32
38    description: |
39      Number of bits per transfer
40
41  xlnx,startup-block:
42    type: boolean
43    description: |
44      Indicates the core is instantiated with the STARTUP block option, as is
45      typically used when interfacing with the FPGA's configuration flash
46      device. In this configuration the SPI clock is routed through the
47      STARTUP block rather than normal signal routing.
48      In this case, a workaround is required to issue a dummy
49      transaction to the SPI flash device to ensure the STARTUP block is
50      disengaged and allow the SPI core to control the CCLK line properly.
51      The dummy READ_ID transaction will be issued to chip select 0.
52
53  fifo-size:
54    type: int
55    description: |
56      FIFO size configured in SPI core. 0 indicates no FIFO.
57      If not specified, 0 is assumed.
58      Used to optimize TX/RX read handling. If the FIFO size is 0, the driver
59      will check for FIFO full/empty after every word.
60