| /Zephyr-latest/drivers/counter/ |
| D | counter_timer_shell.c | 4 * SPDX-License-Identifier: Apache-2.0
47 shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]); in parse_device()
48 return -ENODEV; in parse_device()
63 /* start timer in free running mode */ in cmd_timer_free_running()
70 shell_info(shctx, "%s: Timer is freerunning", argv[ARGV_DEV]); in cmd_timer_free_running()
91 shell_info(shctx, "Timer Stopped"); in cmd_timer_stop()
93 shell_error(shctx, "Failed to stop timer"); in cmd_timer_stop()
94 return -EIO; in cmd_timer_stop()
120 return -ERANGE; in cmd_timer_oneshot()
129 return -ERANGE; in cmd_timer_oneshot()
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| D | counter_smartbond_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
28 #define COUNTER_DT_DEVICE(_idx) DEVICE_DT_GET_OR_NULL(DT_NODELABEL(timer##_idx))
50 /* Register set for timer */
51 TIMER2_Type *timer; member
53 /* Timer driven by DIVn if 1 or lp_clk if 0 */
83 * a timer block will automatically be switched from DIVN to LP and vice versa.
87 const struct counter_smartbond_config *config = dev->config; in counter_smartbond_is_sleep_allowed()
90 (dev == COUNTER_DT_DEVICE(2))) && !config->clock_src_divn); in counter_smartbond_is_sleep_allowed()
96 const struct counter_smartbond_config *config = dev->config; in counter_smartbond_pdc_trigger_get()
98 switch ((uint32_t)config->timer) { in counter_smartbond_pdc_trigger_get()
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| D | counter_nrfx_timer.c | 2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
18 #define CC_TO_ID(cc_num) (cc_num - 2)
50 NRF_TIMER_Type *timer; member
62 const struct counter_nrfx_config *config = dev->config; in start()
64 nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_START); in start()
71 const struct counter_nrfx_config *config = dev->config; in stop()
73 nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_STOP); in stop()
80 const struct counter_nrfx_config *config = dev->config; in get_top_value()
82 return nrf_timer_cc_get(config->timer, TOP_CH); in get_top_value()
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| D | counter_ll_stm32_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
21 /* L0 series MCUs only have 16-bit timers and don't have below macro defined */
26 /** Maximum number of timer channels. */
29 /** Number of channels for timer by index. */
105 TIM_TypeDef *timer; member
118 const struct counter_stm32_config *config = dev->config; in counter_stm32_start()
119 TIM_TypeDef *timer = config->timer; in counter_stm32_start() local
122 LL_TIM_EnableCounter(timer); in counter_stm32_start()
129 const struct counter_stm32_config *config = dev->config; in counter_stm32_stop()
130 TIM_TypeDef *timer = config->timer; in counter_stm32_stop() local
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| D | counter_mcux_qtmr.c | 2 * Copyright (c) 2022 KT-Elektronik, Klaucke und Partner GmbH
3 * SPDX-License-Identifier: Apache-2.0
9 * Counter driver for the Quad Timer through the MCUxpresso SDK. Based mainly on counter_mcux_gpt.c
11 * Each quad timer module has four channels (0-3) that can operate independently, but the Zephyr
12 * counter-API does not support starting or stopping different channels independently. Hence, each
50 * @brief ISR for a specific timer channel
52 * @param dev timer channel device
56 const struct mcux_qtmr_config *config = dev->config; in mcux_qtmr_timer_handler()
57 struct mcux_qtmr_data *data = dev->data; in mcux_qtmr_timer_handler()
58 uint32_t current = QTMR_GetCurrentTimerCount(config->base, config->channel); in mcux_qtmr_timer_handler()
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| D | counter_renesas_ra_agt.c | 4 * SPDX-License-Identifier: Apache-2.0
51 uint32_t period; /* Current timer period (counts) */
52 uint32_t period_counts; /* Period in raw timer counts */
55 /* Alarm-related data */
74 reg->AGTCR = AGT_AGTCR_START_TIMER; in counter_ra_agt_start()
76 while (!(reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) in counter_ra_agt_start()
79 return timeout > 0 ? 0 : -EIO; in counter_ra_agt_start()
87 reg->AGTCR = AGT_AGTCR_STOP_TIMER; in counter_ra_agt_stop()
89 while ((reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) in counter_ra_agt_stop()
92 return timeout > 0 ? 0 : -EIO; in counter_ra_agt_stop()
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| D | counter_max32_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
44 const struct max32_tmr_config *cfg = dev->config; in api_start()
46 Wrap_MXC_TMR_EnableInt(cfg->regs); in api_start()
47 MXC_TMR_Start(cfg->regs); in api_start()
54 const struct max32_tmr_config *cfg = dev->config; in api_stop()
56 Wrap_MXC_TMR_DisableInt(cfg->regs); in api_stop()
57 MXC_TMR_Stop(cfg->regs); in api_stop()
64 const struct max32_tmr_config *cfg = dev->config; in api_get_value()
66 *ticks = MXC_TMR_GetCount(cfg->regs); in api_get_value()
72 const struct max32_tmr_config *cfg = dev->config; in api_set_top_value()
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| D | counter_dw_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
20 /* DW APB timer register offsets */
30 /* DW APB timer control flags */
35 /* DW APB timer modes */
39 #define DEV_CFG(_dev) ((const struct counter_dw_timer_config *)(_dev)->config)
40 #define DEV_DATA(_dev) ((struct counter_dw_timer_drv_data *const)(_dev)->data)
48 /* clock frequency of timer */
53 /* identifier for timer to get clock freq from clk manager */
71 /* clock frequency of timer */
90 counter_alarm_callback_t alarm_cb = data->alarm_cb; in counter_dw_timer_irq_handler()
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| /Zephyr-latest/drivers/watchdog/ |
| D | Kconfig.it8xxx2 | 2 # SPDX-License-Identifier: Apache-2.0
5 bool "ITE it8xxx2 Watchdog Timer (WDT) driver"
10 This option enables the Watchdog Timer driver for ITE it8xxx2.
11 This driver supports only one channel that id is 0 and 16-bits
27 Once warning timer triggered, if watchdog timer isn't reloaded,
28 then we will reduce interval of warning timer to 30ms to print
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| D | wdt_ite_it8xxx2.c | 3 * SPDX-License-Identifier: Apache-2.0
42 const struct wdt_it8xxx2_config *const wdt_config = dev->config; in wdt_it8xxx2_install_timeout()
43 struct wdt_it8xxx2_data *data = dev->data; in wdt_it8xxx2_install_timeout()
44 struct wdt_it8xxx2_regs *const inst = wdt_config->base; in wdt_it8xxx2_install_timeout()
47 if ((inst->ETWCFG) & IT8XXX2_WDT_LEWDCNTL) { in wdt_it8xxx2_install_timeout()
48 return -EBUSY; in wdt_it8xxx2_install_timeout()
55 if ((config->window.min != 0) || (config->window.max == 0)) { in wdt_it8xxx2_install_timeout()
56 data->timeout_installed = false; in wdt_it8xxx2_install_timeout()
57 return -EINVAL; in wdt_it8xxx2_install_timeout()
61 data->timeout = config->window.max; in wdt_it8xxx2_install_timeout()
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| D | wdt_npcx.c | 4 * SPDX-License-Identifier: Apache-2.0
14 * clocks and interrupts (T0 Timer) used for its callback functions in the
18 * +---------------------+ +-----------------+
19 * LFCLK --->| T0 Prescale Counter |-+->| 16-Bit T0 Timer |--------> T0 Timer
21 * +---------------------+ | +-----------------+
22 * +---------------------------------+
24 * | +-------------------+ +-----------------+
25 * +--->| Watchdog Prescale |--->| 8-Bit Watchdog |-----> Watchdog Event/Reset
27 * +-------------------+ +-----------------+
49 * Maximum watchdog window time. Keep the timer and watchdog clock prescaler
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| /Zephyr-latest/tests/boards/nrf52_bsim/egu/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
55 zassert_equal((size_t)&EGU[i]->TASKS_TRIGGER[j], in ZTEST()
77 zassert_equal((size_t)&EGU[i]->EVENTS_TRIGGERED[j], in ZTEST()
102 bool triggered[EGU5_CH_NUM]; member
114 event_triggered_flag.triggered[i] = nrf_egu_event_check(NRF_EGU5, check_event); in SWI5_trigger_function()
115 if (event_triggered_flag.triggered[i]) { in SWI5_trigger_function()
139 zassert_false(event_triggered_flag.triggered[i], "Event %i has been triggered", i); in ZTEST()
143 "event has not been triggered"); in ZTEST()
148 "event %d has been triggered, but it shouldn't", i); in ZTEST()
172 zassert_true(event_triggered_flag.triggered[0], "Event 0 has not been triggered"); in ZTEST()
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| /Zephyr-latest/doc/services/task_wdt/ |
| D | index.rst | 9 Many microcontrollers feature a hardware watchdog timer peripheral. Its purpose
11 malfunctions. Once initialized, the watchdog timer has to be restarted ("fed")
14 triggered to bring the system back to normal operation.
16 In real-time operating systems with multiple tasks running in parallel, a
24 The task watchdog uses a kernel timer as its backend. If configured properly,
25 the timer ISR is never actually called during normal operation, as the timer is
|
| /Zephyr-latest/tests/boards/nrf/mram_latency/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
36 req->res = res; in basic_cb()
37 req->state = state; in basic_cb()
38 k_sem_give(&req->sem); in basic_cb()
58 /* Req: 0->1 trigger to on */ in ZTEST()
64 /* Req: 1->2 */ in ZTEST()
80 /* Req: 2->1 */ in ZTEST()
83 /* Req: 1->0 going to off triggered*/ in ZTEST()
90 /* Req: 0->1 triggered to on while in to off. */ in ZTEST()
94 /* Req: 1->0 releases which to off. */ in ZTEST()
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| /Zephyr-latest/dts/bindings/watchdog/ |
| D | ti,tps382x.yaml | 10 wdi-gpios:
11 type: phandle-array
15 then reset is triggered. The reset has a typical delay time of 200 ms for
16 TPS3823/4/8, TPS3823A. The timer clears when reset is asserted or
21 timeout-period:
25 Time-out period in milliseconds. Typical for TPS3823/4/8 and TPS3823A is
|
| /Zephyr-latest/doc/develop/api/ |
| D | design_guidelines.rst | 43 timer alarm fires are satisfied by::
45 void handle_timeout(struct k_timer *timer)
49 timer is embedded in a structure reachable from
63 counter channel timed-out and the counter value at which the timeout
92 the unsupported API will result in a link-time error.
99 other content the feature-specific code should be conditionally
114 - APIs that are supported but not implemented shall return ``-ENOSYS``.
116 - Optional APIs that are not supported by the hardware should be implemented and
117 the return code in this case shall be ``-ENOTSUP``.
119 - When an API is implemented, but the particular combination of options
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| /Zephyr-latest/drivers/timer/ |
| D | ite_it8xxx2_timer.c | 3 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/timer/system_timer.h>
10 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
17 LOG_MODULE_REGISTER(timer, LOG_LEVEL_ERR);
19 #define COUNT_1US (EC_FREQ / USEC_PER_SEC - 1)
22 "ITE RTOS timer HW frequency is fixed at 32768Hz");
24 /* Event timer configurations */
28 /* Event timer max count is 512 sec (base on clock source 32768Hz) */
31 /* Busy wait low timer configurations */
36 /* Busy wait high timer configurations */
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| D | arcv2_timer0.c | 2 * Copyright (c) 2014-2015 Wind River Systems, Inc.
5 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/timer/system_timer.h>
18 * use secure Timer 0
43 /* arc timer has 32 bit, here use 31 bit to avoid the possible
51 #define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
73 * This local variable holds the amount of timer cycles elapsed
78 * HW timer is calculated as:
93 * timer wraps ('overflows') and is used in the calculation
165 * timer wraps (overflows).
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| D | cortex_m_systick.c | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/drivers/timer/system_timer.h>
20 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
25 * reliably" -- it becomes the minimum value of the LOAD register, and
50 * HW timer is calculated as:
61 * Additions/subtractions/comparisons of 64-bits values on 32-bits systems
63 * cycle_count and announced_cycles is stored in a 32-bit variable before
70 * SysTick timer wraps ('overflows') and is used in the calculation
83 * It is used for chips that has to use a separate idle timer in such
84 * case because the Cortex-m SysTick is not clocked in the low power
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| D | intel_adsp_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/drivers/timer/system_timer.h>
12 #include <cavs-idc.h>
21 * @brief Intel Audio DSP Wall Clock Timer driver
23 * The Audio DSP on Intel SoC has a timer with one counter and two compare
24 * registers that is external to the CPUs. This timer is accessible from
25 * all available CPU cores and provides a synchronized timer under SMP.
39 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
72 /* Arm the timer */ in set_compare()
112 dticks = (curr - last_count) / CYC_PER_TICK; in compare_isr()
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| D | cc13xx_cc26xx_rtc_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
10 * TI SimpleLink CC13X2/CC26X2 RTC-based system timer
12 * This system timer implementation supports both tickless and ticking modes.
13 * RTC counts continually in 64-bit mode and timeouts are
14 * scheduled using the RTC comparator. An interrupt is triggered whenever
21 #include <zephyr/drivers/timer/system_timer.h>
33 /* Number of counts per rtc timer cycle */
80 if ((next - now) > (uint32_t)0x80000000) { in setThreshold()
83 } else if ((now + COMPARE_MARGIN - next) < (uint32_t)0x80000000) { in setThreshold()
111 ticks = (currCount - rtc_last) / RTC_COUNTS_PER_TICK; in rtc_isr()
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| D | npcx_itim_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
14 * 64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timers, the
18 * - A system timer based on an ITIM64 (Internal 64-bit timer) instance, clocked
20 * - Provide a 64-bit cycles reading and ticks computation based on it.
21 * - Its prescaler is set to 1 and provide the kernel cycles reading without
23 * - After ec entered "sleep/deep sleep" power state which is used for better
26 * - A event timer based on an ITIM32 (Internal 32-bit timer) instance, clocked
29 * - Provide a system clock timeout notification. In its ISR, the driver informs
31 * - Its prescaler is set to 1 and the formula between event timer's cycles and
33 * - Compensate reading of ITIM64 which clock is gating after ec entered
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| /Zephyr-latest/dts/bindings/tcpc/ |
| D | nuvoton,numaker-tcpc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton NuMaker USB Type-C port controller
6 compatible: "nuvoton,numaker-tcpc"
8 include: [base.yaml, reset-device.yaml, pinctrl-device.yaml]
23 vconn-overcurrent-event-polarity:
28 - "low-active"
29 - "high-active"
31 vconn-discharge-polarity:
36 - "low-active"
37 - "high-active"
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,stm32-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-qdec"
9 - name: base.yaml
10 - name: pinctrl-device.yaml
13 pinctrl-0:
16 pinctrl-names:
19 st,encoder-mode:
34 Default value complies with stm32 low level timer encoder init value.
37 - 0x1
38 - 0x2
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| /Zephyr-latest/drivers/sensor/renesas/isl29035/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
20 Priority of thread used to handle the timer and threshold triggers.
97 depends on $(dt_compat_any_has_prop,$(DT_COMPAT_ISIL_ISL29035),int-gpios)
103 depends on $(dt_compat_any_has_prop,$(DT_COMPAT_ISIL_ISL29035),int-gpios)
132 to be triggered.
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