Lines Matching +full:timer +full:- +full:triggered

4  * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/drivers/timer/system_timer.h>
12 #include <cavs-idc.h>
21  * @brief Intel Audio DSP Wall Clock Timer driver
23  * The Audio DSP on Intel SoC has a timer with one counter and two compare
24  * registers that is external to the CPUs. This timer is accessible from
25  * all available CPU cores and provides a synchronized timer under SMP.
39 #define MAX_TICKS	((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
72 	/* Arm the timer */  in set_compare()
112 	dticks = (curr - last_count) / CYC_PER_TICK;  in compare_isr()
114 	/* Clear the triggered bit */  in compare_isr()
123 	if ((int64_t)(next - curr) < MIN_DELAY) {  in compare_isr()
140 	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);  in sys_clock_set_timeout()
148 	adj = (uint32_t)(curr - last_count) + (CYC_PER_TICK - 1);  in sys_clock_set_timeout()
149 	if (cyc <= MAX_CYC - adj) {  in sys_clock_set_timeout()
157 	if (((uint32_t)next - (uint32_t)curr) < MIN_DELAY) {  in sys_clock_set_timeout()
172 	uint64_t ret = (count() - last_count) / CYC_PER_TICK;  in sys_clock_elapsed()
188 /* Interrupt setup is partially-cpu-local state, so needs to be
190  * the Zephyr convention of sending timer interrupts to all cpus (for
195 	int cpu = arch_curr_cpu()->id;  in irq_init()
198 	 * (for per-core control) above the interrupt controller.  in irq_init()