Lines Matching +full:timer +full:- +full:triggered
4 * SPDX-License-Identifier: Apache-2.0
21 /* L0 series MCUs only have 16-bit timers and don't have below macro defined */
26 /** Maximum number of timer channels. */
29 /** Number of channels for timer by index. */
105 TIM_TypeDef *timer; member
118 const struct counter_stm32_config *config = dev->config; in counter_stm32_start()
119 TIM_TypeDef *timer = config->timer; in counter_stm32_start() local
122 LL_TIM_EnableCounter(timer); in counter_stm32_start()
129 const struct counter_stm32_config *config = dev->config; in counter_stm32_stop()
130 TIM_TypeDef *timer = config->timer; in counter_stm32_stop() local
133 LL_TIM_DisableCounter(timer); in counter_stm32_stop()
140 const struct counter_stm32_config *config = dev->config; in counter_stm32_get_top_value()
142 return LL_TIM_GetAutoReload(config->timer); in counter_stm32_get_top_value()
147 const struct counter_stm32_config *config = dev->config; in counter_stm32_read()
149 return LL_TIM_GetCounter(config->timer); in counter_stm32_read()
166 to_top = top - val1; in counter_stm32_ticks_add()
168 return (val2 <= to_top) ? val1 + val2 : val2 - to_top - 1U; in counter_stm32_ticks_add()
174 return (val - old) & top; in counter_stm32_ticks_sub()
177 /* if top is not 2^n-1 */ in counter_stm32_ticks_sub()
178 return (val >= old) ? (val - old) : val + top + 1U - old; in counter_stm32_ticks_sub()
183 const struct counter_stm32_config *config = dev->config; in counter_stm32_counter_stm32_set_cc_int_pending()
184 struct counter_stm32_data *data = dev->data; in counter_stm32_counter_stm32_set_cc_int_pending()
186 atomic_or(&data->cc_int_pending, BIT(chan)); in counter_stm32_counter_stm32_set_cc_int_pending()
187 NVIC_SetPendingIRQ(config->irqn); in counter_stm32_counter_stm32_set_cc_int_pending()
193 const struct counter_stm32_config *config = dev->config; in counter_stm32_set_cc()
194 struct counter_stm32_data *data = dev->data; in counter_stm32_set_cc()
196 __ASSERT_NO_MSG(data->guard_period < counter_stm32_get_top_value(dev)); in counter_stm32_set_cc()
197 uint32_t val = alarm_cfg->ticks; in counter_stm32_set_cc()
198 uint32_t flags = alarm_cfg->flags; in counter_stm32_set_cc()
201 TIM_TypeDef *timer = config->timer; in counter_stm32_set_cc() local
209 __ASSERT(!check_it_enabled[id](timer), in counter_stm32_set_cc()
217 prev_val = get_timer_compare[id](timer); in counter_stm32_set_cc()
218 set_timer_compare[id](timer, now); in counter_stm32_set_cc()
219 clear_it_flag[id](timer); in counter_stm32_set_cc()
222 max_rel_val = top - data->guard_period; in counter_stm32_set_cc()
228 * setting is detected, interrupt shall be triggered for in counter_stm32_set_cc()
229 * immediate expiration of the timer. Detection is performed in counter_stm32_set_cc()
240 set_timer_compare[id](timer, val); in counter_stm32_set_cc()
245 diff = counter_stm32_ticks_sub(val - 1U, counter_stm32_read(dev), top); in counter_stm32_set_cc()
248 err = -ETIME; in counter_stm32_set_cc()
251 /* Interrupt is triggered always for relative alarm and in counter_stm32_set_cc()
257 config->ch_data[id].callback = NULL; in counter_stm32_set_cc()
260 enable_it[id](timer); in counter_stm32_set_cc()
269 const struct counter_stm32_config *config = dev->config; in counter_stm32_set_alarm()
270 struct counter_stm32_ch_data *chdata = &config->ch_data[chan]; in counter_stm32_set_alarm()
272 if (alarm_cfg->ticks > counter_stm32_get_top_value(dev)) { in counter_stm32_set_alarm()
273 return -EINVAL; in counter_stm32_set_alarm()
276 if (chdata->callback) { in counter_stm32_set_alarm()
277 return -EBUSY; in counter_stm32_set_alarm()
280 chdata->callback = alarm_cfg->callback; in counter_stm32_set_alarm()
281 chdata->user_data = alarm_cfg->user_data; in counter_stm32_set_alarm()
288 const struct counter_stm32_config *config = dev->config; in counter_stm32_cancel_alarm()
290 disable_it[chan](config->timer); in counter_stm32_cancel_alarm()
291 config->ch_data[chan].callback = NULL; in counter_stm32_cancel_alarm()
299 const struct counter_stm32_config *config = dev->config; in counter_stm32_set_top_value()
300 TIM_TypeDef *timer = config->timer; in counter_stm32_set_top_value() local
301 struct counter_stm32_data *data = dev->data; in counter_stm32_set_top_value()
308 if (config->ch_data[i].callback) { in counter_stm32_set_top_value()
309 return -EBUSY; in counter_stm32_set_top_value()
313 LL_TIM_DisableIT_UPDATE(timer); in counter_stm32_set_top_value()
314 LL_TIM_SetAutoReload(timer, cfg->ticks); in counter_stm32_set_top_value()
315 LL_TIM_ClearFlag_UPDATE(timer); in counter_stm32_set_top_value()
317 data->top_cb = cfg->callback; in counter_stm32_set_top_value()
318 data->top_user_data = cfg->user_data; in counter_stm32_set_top_value()
320 if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) { in counter_stm32_set_top_value()
321 LL_TIM_SetCounter(timer, 0); in counter_stm32_set_top_value()
322 } else if (counter_stm32_read(dev) >= cfg->ticks) { in counter_stm32_set_top_value()
323 err = -ETIME; in counter_stm32_set_top_value()
324 if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) { in counter_stm32_set_top_value()
325 LL_TIM_SetCounter(timer, 0); in counter_stm32_set_top_value()
329 if (cfg->callback) { in counter_stm32_set_top_value()
330 LL_TIM_EnableIT_UPDATE(timer); in counter_stm32_set_top_value()
338 const struct counter_stm32_config *cfg = dev->config; in counter_stm32_get_pending_int()
343 pending |= LL_TIM_IsActiveFlag_CC4(cfg->timer); in counter_stm32_get_pending_int()
346 pending |= LL_TIM_IsActiveFlag_CC3(cfg->timer); in counter_stm32_get_pending_int()
349 pending |= LL_TIM_IsActiveFlag_CC2(cfg->timer); in counter_stm32_get_pending_int()
352 pending |= LL_TIM_IsActiveFlag_CC1(cfg->timer); in counter_stm32_get_pending_int()
359 * Obtain timer clock speed.
361 * @param pclken Timer clock control subsystem.
362 * @param tim_clk Where computed timer clock will be stored.
377 return -ENODEV; in counter_stm32_get_tim_clk()
387 if (pclken->bus == STM32_CLOCK_BUS_APB1) { in counter_stm32_get_tim_clk()
393 if (pclken->bus == STM32_CLOCK_BUS_APB1) { in counter_stm32_get_tim_clk()
395 apb_psc = (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV)); in counter_stm32_get_tim_clk()
403 apb_psc = (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV)); in counter_stm32_get_tim_clk()
418 * Up to a certain threshold value of APB{1,2} prescaler, timer clock in counter_stm32_get_tim_clk()
420 * (2 if TIMPRE=0, 4 if TIMPRE=1). Above threshold, timer clock is set in counter_stm32_get_tim_clk()
448 * If the APB prescaler equals 1, the timer clock frequencies in counter_stm32_get_tim_clk()
465 const struct counter_stm32_config *cfg = dev->config; in counter_stm32_init_timer()
466 struct counter_stm32_data *data = dev->data; in counter_stm32_init_timer()
467 TIM_TypeDef *timer = cfg->timer; in counter_stm32_init_timer() local
474 (clock_control_subsys_t)&cfg->pclken); in counter_stm32_init_timer()
479 r = counter_stm32_get_tim_clk(&cfg->pclken, &tim_clk); in counter_stm32_init_timer()
481 LOG_ERR("Could not obtain timer clock (%d)", r); in counter_stm32_init_timer()
484 data->freq = tim_clk / (cfg->prescaler + 1U); in counter_stm32_init_timer()
486 if (!device_is_ready(cfg->reset.dev)) { in counter_stm32_init_timer()
488 return -ENODEV; in counter_stm32_init_timer()
491 /* Reset timer to default state using RCC */ in counter_stm32_init_timer()
492 (void)reset_line_toggle_dt(&cfg->reset); in counter_stm32_init_timer()
495 cfg->irq_config_func(dev); in counter_stm32_init_timer()
497 /* initialize timer */ in counter_stm32_init_timer()
500 init.Prescaler = cfg->prescaler; in counter_stm32_init_timer()
505 if (LL_TIM_Init(timer, &init) != SUCCESS) { in counter_stm32_init_timer()
506 LOG_ERR("Could not initialize timer"); in counter_stm32_init_timer()
507 return -EIO; in counter_stm32_init_timer()
515 struct counter_stm32_data *data = dev->data; in counter_stm32_get_guard_period()
518 return data->guard_period; in counter_stm32_get_guard_period()
524 struct counter_stm32_data *data = dev->data; in counter_stm32_set_guard_period()
529 data->guard_period = guard; in counter_stm32_set_guard_period()
535 struct counter_stm32_data *data = dev->data; in counter_stm32_get_freq()
537 return data->freq; in counter_stm32_get_freq()
542 struct counter_stm32_data *data = dev->data; in counter_stm32_top_irq_handle()
544 counter_top_callback_t cb = data->top_cb; in counter_stm32_top_irq_handle()
546 __ASSERT(cb != NULL, "top event enabled - expecting callback"); in counter_stm32_top_irq_handle()
547 cb(dev, data->top_user_data); in counter_stm32_top_irq_handle()
552 const struct counter_stm32_config *config = dev->config; in counter_stm32_alarm_irq_handle()
553 struct counter_stm32_data *data = dev->data; in counter_stm32_alarm_irq_handle()
554 TIM_TypeDef *timer = config->timer; in counter_stm32_alarm_irq_handle() local
559 atomic_and(&data->cc_int_pending, ~BIT(id)); in counter_stm32_alarm_irq_handle()
560 disable_it[id](timer); in counter_stm32_alarm_irq_handle()
562 chdata = &config->ch_data[id]; in counter_stm32_alarm_irq_handle()
563 cb = chdata->callback; in counter_stm32_alarm_irq_handle()
564 chdata->callback = NULL; in counter_stm32_alarm_irq_handle()
567 uint32_t cc_val = get_timer_compare[id](timer); in counter_stm32_alarm_irq_handle()
569 cb(dev, id, cc_val, chdata->user_data); in counter_stm32_alarm_irq_handle()
589 bool hw_irq = LL_TIM_IsActiveFlag_CC##cc(timer) && \
590 LL_TIM_IsEnabledIT_CC##cc(timer); \
591 if (hw_irq || (data->cc_int_pending & BIT(cc - 1U))) { \
593 LL_TIM_ClearFlag_CC##cc(timer); \
595 counter_stm32_alarm_irq_handle(dev, cc - 1U); \
601 const struct counter_stm32_config *config = dev->config; in counter_stm32_irq_handler()
602 struct counter_stm32_data *data = dev->data; in counter_stm32_irq_handler()
603 TIM_TypeDef *timer = config->timer; in counter_stm32_irq_handler() local
608 TIM_IRQ_HANDLE_CC(timer, 4); in counter_stm32_irq_handler()
611 TIM_IRQ_HANDLE_CC(timer, 3); in counter_stm32_irq_handler()
614 TIM_IRQ_HANDLE_CC(timer, 2); in counter_stm32_irq_handler()
617 TIM_IRQ_HANDLE_CC(timer, 1); in counter_stm32_irq_handler()
621 if (LL_TIM_IsActiveFlag_UPDATE(timer) && LL_TIM_IsEnabledIT_UPDATE(timer)) { in counter_stm32_irq_handler()
622 LL_TIM_ClearFlag_UPDATE(timer); in counter_stm32_irq_handler()
627 #define TIMER(idx) DT_INST_PARENT(idx) macro
630 #define TIM(idx) ((TIM_TypeDef *)DT_REG_ADDR(TIMER(idx)))
633 BUILD_ASSERT(DT_PROP(TIMER(idx), st_prescaler) <= 0xFFFF, \
634 "TIMER prescaler out of range"); \
636 "TIMER too many channels"); \
643 IRQ_CONNECT(DT_IRQN(TIMER(idx)), \
644 DT_IRQ(TIMER(idx), priority), \
648 irq_enable(DT_IRQN(TIMER(idx))); \
660 .timer = TIM(idx), \
661 .prescaler = DT_PROP(TIMER(idx), st_prescaler), \
663 .bus = DT_CLOCKS_CELL(TIMER(idx), bus), \
664 .enr = DT_CLOCKS_CELL(TIMER(idx), bits) \
667 .irqn = DT_IRQN(TIMER(idx)), \
668 .reset = RESET_DT_SPEC_GET(TIMER(idx)), \