Searched full:syscfg (Results 1 – 15 of 15) sorted by relevance
6 compatible: "gd,gd32-syscfg"
29 /* HW semaphore and SysCfg Clock enable */ in stm32h7_m4_wakeup()33 if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) { in stm32h7_m4_wakeup()
50 syscfg: syscfg@40010000 { label51 compatible = "gd,gd32-syscfg";
181 syscfg: syscfg@40010000 { label182 compatible = "gd,gd32-syscfg";
158 /* SYSCFG is required to remap IRQ to avoid conflicts with CAN */ in config_enable_default_clocks()
300 /* CLK_SYS peripherals: SYSCFG */ in get_apb0_periph_clkrate()722 /* Unconditionally enable SYSCFG clock for other drivers */ in stm32_clock_control_init()
777 * The SYSCFG is needed to control VREFINT, so clock it. in set_up_fixed_clock_sources()
20 /** SYSCFG DT node */21 #define SYSCFG_NODE DT_NODELABEL(syscfg)
230 Enable GD32 System Configuration (SYSCFG) HAL module driver
258 syscfg: syscfg@40013800 { label259 compatible = "gd,gd32-syscfg";
143 * The 'reg' property corresponds to the SYSCFG memory range,
298 /* Set the OTG PHY reference clock selection (through SYSCFG) block */ in usb_dc_stm32_phy_specific_clock_enable()306 /* Configuring the SYSCFG registers OTG_HS PHY : OTG_HS PHY enable*/ in usb_dc_stm32_phy_specific_clock_enable()
995 /* Set the OTG PHY reference clock selection (through SYSCFG) block */ in priv_clock_enable()998 /* Configuring the SYSCFG registers OTG_HS PHY : OTG_HS PHY enable*/ in priv_clock_enable()
72 SYSCFG->CFGR1 |= SYSCFG_CFGR1_UCPD1_STROBE_Msk; in update_stm32g0x_cc_line()74 SYSCFG->CFGR1 |= SYSCFG_CFGR1_UCPD2_STROBE_Msk; in update_stm32g0x_cc_line()
1219 * :dtcompatible:`gd,gd32-syscfg`
