Searched full:sse (Results 1 – 25 of 37) sorted by relevance
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| /Zephyr-latest/soc/arm/musca/ |
| D | Kconfig.soc | 14 ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1
20 ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-S1
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| /Zephyr-latest/soc/arm/mps2/ |
| D | Kconfig.soc | 24 ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0
30 ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1
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| /Zephyr-latest/tests/kernel/fpu_sharing/float_disable/ |
| D | testcase.yaml | 26 kernel.fpu_sharing.float_disable.x86.fpu.sse:
40 kernel.fpu_sharing.float_disable.x86.sse:
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| /Zephyr-latest/arch/x86/core/ia32/ |
| D | float.c | 27 * the stack size requirements of all other threads. Also, the SSE registers
49 /* SSE control/status register default value (used by assembler code) */
76 * specified area. If the specified thread supports SSE then
92 * specified area. If the specified thread supports SSE then
115 * @brief Initialize SSE register context information.
117 * This routine initializes the system's "live" SSE registers.
128 * specified thread control block. The SSE registers are saved only if the
146 * The SSE registers are initialized only if the thread is actually using them.
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| D | crt0.S | 172 * Permit use of SSE instructions
174 * Note that all SSE exceptions are masked by default,
175 * and that _no_ handler for SSE exceptions (#XM) is provided.
183 /* initialize SSE control/status reg */
295 /* SSE control & status register initial value */
298 .long 0x1f80 /* all SSE exceptions clear & masked */
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| /Zephyr-latest/doc/kernel/services/other/ |
| D | float.rst | 27 which are described below. In addition, the kernel's support for the SSE
66 * SSE user: A thread that can use both the standard floating point registers
67 and SSE registers
73 or SSE user are not impacted by the computations performed by the other users.
257 FPU user or SSE user on a case-by-case basis. A "lazy save" algorithm is used
270 preemptive SSE 464 bytes
275 The thread is tagged as an SSE user if the kernel has been configured
276 to support the SSE registers, or as an FPU user if the SSE registers are
278 tagged as an SSE user, or if the application wants to avoid the exception
295 :c:func:`k_float_disable` to remove its tagging as an FPU user or SSE user.
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| /Zephyr-latest/tests/kernel/fpu_sharing/generic/ |
| D | testcase.yaml | 74 kernel.fpu_sharing.generic.x86.fpu.sse:
91 kernel.fpu_sharing.generic.x86.sse:
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| /Zephyr-latest/arch/x86/core/intel64/ |
| D | thread.c | 72 /* x86-64 always has FP/SSE enabled so cannot be disabled */ in arch_float_disable()
80 /* x86-64 always has FP/SSE enabled so nothing to do here */ in arch_float_enable()
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| /Zephyr-latest/arch/x86/ |
| D | ia32.cmake | 35 zephyr_cc_option(-mfpmath=sse)
77 zephyr_cc_option(-mno-sse)
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| D | intel64.cmake | 13 # x86-64 by default has SSE and SSE2
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| D | Kconfig | 114 bool "SSE Support"
117 This option enables SSE support, and the use of SSE registers
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| /Zephyr-latest/include/zephyr/arch/x86/intel64/ |
| D | thread.h | 34 * Some SSE definitions. Ideally these will ultimately be shared with 32-bit.
147 char __aligned(X86_FXSAVE_ALIGN) sse[X86_FXSAVE_SIZE];
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| /Zephyr-latest/arch/x86/core/ |
| D | Kconfig.ia32 | 101 config SSE config
102 bool "SSE registers"
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| /Zephyr-latest/drivers/ipm/ |
| D | Kconfig | 16 Driver for SSE 200 MHU (Message Handling Unit)
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| D | ipm_mhu.h | 23 /* SSE 200 MHU register map structure */
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| /Zephyr-latest/arch/x86/core/offsets/ |
| D | intel64_offsets.c | 28 GEN_OFFSET_SYM(_thread_arch_t, sse);
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| /Zephyr-latest/arch/x86/include/ |
| D | kernel_arch_data.h | 58 #define CR4_OSFXSR BIT(9) /* enable SSE (OS FXSAVE/RSTOR) */
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| /Zephyr-latest/boards/arm/mps3/doc/ |
| D | index.rst | 190 Soft Macro Model (SMM) implementation of SSE-300 subsystem
192 Soft Macro Model (SMM) implementation of SSE-310 subsystem
349 - `Corelink SSE-300 Example Subsystem`_
350 - `Corelink SSE-310 Example Subsystem`_
379 .. _Corelink SSE-300 Example Subsystem:
382 .. _Corelink SSE-310 Example Subsystem:
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| /Zephyr-latest/arch/posix/ |
| D | CMakeLists.txt | 63 # (clang defaults to use SSE, but, setting this option for it is safe)
64 check_set_compiler_property(APPEND PROPERTY fpsse2 "SHELL:-msse2 -mfpmath=sse")
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| /Zephyr-latest/boards/qemu/x86/ |
| D | board.cmake | 40 string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse")
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| /Zephyr-latest/boards/arm/v2m_musca_b1/doc/ |
| D | index.rst | 226 multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The
280 For more details please refer to `Corelink SSE-200 Subsystem`_.
398 .. _Corelink SSE-200 Subsystem:
399 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
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| /Zephyr-latest/boards/arm/v2m_musca_s1/doc/ |
| D | index.rst | 220 multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The
274 For more details please refer to `Corelink SSE-200 Subsystem`_.
426 .. _Corelink SSE-200 Subsystem:
427 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
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| /Zephyr-latest/subsys/debug/ |
| D | thread_info.c | 118 sse),
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| /Zephyr-latest/boards/arm/mps2/doc/ |
| D | mps2_an521.rst | 106 - Soft Macro Model (SMM) implementation of SSE-200 subsystem
464 For more details refer to `Corelink SSE-200 Subsystem`_.
567 .. _Corelink SSE-200 Subsystem:
568 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
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| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | thread.h | 191 * The following structure defines the set of 'volatile' x87 FPU/MMX/SSE
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