| /Zephyr-latest/dts/bindings/wifi/ |
| D | infineon,airoc-wifi-spi.yaml | 2 AIROC Wi-Fi Connectivity over SPI.
4 compatible: "infineon,airoc-wifi"
6 include: [spi-device.yaml, "infineon,airoc-wifi.yaml"]
9 wifi-host-wake-gpios:
12 bus-select-gpios:
16 wifi-reg-on-gpios goes high to select SPI bus mode.
17 type: phandle-array
19 spi-half-duplex:
21 Use half-duplex communication; if not present, full-
22 duplex operation is assumed.
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | mipi-dbi-spi-device.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI DBI devices using Mode C (SPI)
6 include: [mipi-dbi-device.yaml]
9 duplex:
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
24 SPI clock polarity which indicates the clock idle state.
26 mipi-cpha:
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| D | zephyr,mipi-dbi-spi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 MIPI-DBI Mode C compatible SPI controller. This driver emulates MIPI DBI
6 mode C using a SPI controller and GPIO pins
7 compatible: "zephyr,mipi-dbi-spi"
9 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
12 spi-dev:
16 SPI device to use for data transfers with MIPI DBI commands. This SPI
19 dc-gpios:
20 type: phandle-array
22 Data/command gpio pin. Required when using 4 wire SPI mode (Mode C1).
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| /Zephyr-latest/dts/bindings/spi/ |
| D | espressif,esp32-spi.yaml | 1 description: ESP32 SPI
3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
26 description: Enable dummy SPI compensation cycles
31 Enable 3-wire mode
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| D | spi-device.yaml | 1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for SPI devices
8 on-bus: spi
13 spi-max-frequency:
16 description: Maximum clock frequency of device's SPI interface in Hz
17 duplex:
21 Duplex mode, full or half. By default it's always full duplex thus 0
24 list (see dt-bindings/spi/spi.h)
28 - 0
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| D | microchip,xec-qmspi-ldma.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
44 - 1
45 - 2
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| /Zephyr-latest/include/zephyr/dt-bindings/spi/ |
| D | spi.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * @brief SPI Interface
11 * @defgroup spi_interface SPI Interface
17 * @name SPI duplex mode
20 * Some controllers support half duplex transfer, which results in 3-wire usage.
21 * By default, full duplex will prevail.
28 * @name SPI Frame Format
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_adin2111_priv.h | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/spi.h>
17 /* SPI frequency maximum, based on clock cycle time */
42 /* Receive Cut Through Enable. Must be 0 for Generic SPI */
105 /*!< Mask Bit for P2_RX_RDY. Generic SPI only.*/
107 /*!< Mask Bit for SPI_ERR. Generic SPI only. */
109 /*!< Mask Bit for P1_RX_RDY. Generic SPI only.*/
111 /*!< Mask Bit for TX_FRM_DONE. Generic SPI only.*/
153 /* SPI header size in bytes */
155 /* SPI header size for write transaction */
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| D | eth_enc424j600.c | 1 /* ENC424J600 Stand-alone Ethernet Controller with SPI
7 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/drivers/spi.h>
29 const struct enc424j600_config *config = dev->config; in enc424j600_write_sbc()
40 spi_write_dt(&config->spi, &tx); in enc424j600_write_sbc()
46 const struct enc424j600_config *config = dev->config; in enc424j600_write_sfru()
62 spi_write_dt(&config->spi, &tx); in enc424j600_write_sfru()
68 const struct enc424j600_config *config = dev->config; in enc424j600_read_sfru()
90 if (!spi_transceive_dt(&config->spi, &tx, &rx)) { in enc424j600_read_sfru()
101 const struct enc424j600_config *config = dev->config; in enc424j600_modify_sfru()
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| D | eth_lan9250.c | 1 /* LAN9250 Stand-alone Ethernet Controller with SPI
5 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/drivers/spi.h>
26 const struct lan9250_config *config = dev->config; in lan9250_write_sys_reg()
43 return spi_write_dt(&config->spi, &tx); in lan9250_write_sys_reg()
48 const struct lan9250_config *config = dev->config; in lan9250_read_sys_reg()
72 return spi_transceive_dt(&config->spi, &tx, &rx); in lan9250_read_sys_reg()
89 return -EIO; in lan9250_wait_ready()
141 return -EIO; in lan9250_wait_mac_ready()
155 * https://github.com/microchip-pic-avr-solutions/ethernet-lan9250/ in lan9250_read_phy_reg()
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| /Zephyr-latest/boards/raspberrypi/rpi_pico/ |
| D | rpi_pico_rp2040_w.dts | 2 * Copyright (c) 2023 Dave Rensberger - Beechwoods Software
5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "rpi_pico-common.dtsi"
24 input-enable;
33 input-enable;
42 compatible = "raspberrypi,pico-spi-pio";
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
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| /Zephyr-latest/drivers/spi/ |
| D | spi_numaker.c | 2 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi/rtio.h>
26 SPI_T *spi; member
42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
58 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
59 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure()
62 if (spi_context_configured(&data->ctx, config)) { in spi_numaker_configure()
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| D | spi_xec_qmspi_ldma.c | 4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/spi.h>
19 #include <zephyr/drivers/spi/rtio.h>
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
33 /* MEC172x QMSPI controller SPI Mode 3 signalling has an anomaly where
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
85 uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
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| D | spi_bitbang.c | 2 * Copyright (c) 2021 Marc Reilly - Creative Product Design
4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/drivers/spi.h>
15 #include <zephyr/drivers/spi/rtio.h>
35 if (config->operation & SPI_OP_MODE_SLAVE) { in spi_bitbang_configure()
37 return -ENOTSUP; in spi_bitbang_configure()
40 if (config->operation & (SPI_LINES_DUAL | SPI_LINES_QUAD | SPI_LINES_OCTAL)) { in spi_bitbang_configure()
42 return -ENOTSUP; in spi_bitbang_configure()
45 const int bits = SPI_WORD_SIZE_GET(config->operation); in spi_bitbang_configure()
49 return -ENOTSUP; in spi_bitbang_configure()
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| D | spi_oc_simple.c | 4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/drivers/spi.h>
15 #include <zephyr/drivers/spi/rtio.h>
35 struct spi_oc_simple_data *spi, in spi_oc_simple_configure() argument
41 if (spi_context_configured(&spi->ctx, config)) { in spi_oc_simple_configure()
46 if (config->operation & SPI_HALF_DUPLEX) { in spi_oc_simple_configure()
47 LOG_ERR("Half-duplex not supported"); in spi_oc_simple_configure()
48 return -ENOTSUP; in spi_oc_simple_configure()
51 /* Simple SPI only supports master mode */ in spi_oc_simple_configure()
52 if (spi_context_is_slave(&spi->ctx)) { in spi_oc_simple_configure()
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| D | spi_gecko_eusart.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/spi.h>
46 struct spi_gecko_eusart_data *data = dev->data; in spi_eusart_config()
47 const struct spi_gecko_eusart_config *gecko_config = dev->config; in spi_eusart_config()
55 err = clock_control_get_rate(gecko_config->clock_dev, in spi_eusart_config()
56 (clock_control_subsys_t)&gecko_config->clock_cfg, in spi_eusart_config()
61 /* Max supported SPI frequency is half the source clock */ in spi_eusart_config()
64 if (spi_context_configured(&data->ctx, config)) { in spi_eusart_config()
69 if (config->operation & SPI_HALF_DUPLEX) { in spi_eusart_config()
70 LOG_ERR("Half-duplex not supported"); in spi_eusart_config()
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| D | spi_litex_litespi.c | 4 * SPDX-License-Identifier: Apache-2.0
44 const struct spi_litex_dev_config *dev_config = dev->config; in spi_litex_set_frequency()
46 if (!dev_config->phy_clk_divisor_exists) { in spi_litex_set_frequency()
52 uint32_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), (2 * config->frequency)) - 1; in spi_litex_set_frequency()
54 litex_write32(divisor, dev_config->phy_clk_divisor_addr); in spi_litex_set_frequency()
61 struct spi_litex_data *dev_data = dev->data; in spi_config()
63 if (config->slave != 0) { in spi_config()
64 if (config->slave >= SPI_MAX_CS_SIZE) { in spi_config()
66 return -ENOTSUP; in spi_config()
70 if (config->operation & SPI_HALF_DUPLEX) { in spi_config()
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| D | spi_cc13xx_cc26xx.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/spi.h>
14 #include <zephyr/drivers/spi/rtio.h>
41 const struct spi_cc13xx_cc26xx_config *cfg = dev->config; in spi_cc13xx_cc26xx_configure()
42 struct spi_cc13xx_cc26xx_data *data = dev->data; in spi_cc13xx_cc26xx_configure()
43 struct spi_context *ctx = &data->ctx; in spi_cc13xx_cc26xx_configure()
51 if (config->operation & SPI_HALF_DUPLEX) { in spi_cc13xx_cc26xx_configure()
52 LOG_ERR("Half-duplex not supported"); in spi_cc13xx_cc26xx_configure()
53 return -ENOTSUP; in spi_cc13xx_cc26xx_configure()
57 if (SPI_OP_MODE_GET(config->operation) != SPI_OP_MODE_MASTER) { in spi_cc13xx_cc26xx_configure()
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| D | spi_nrfx_spi.c | 2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/drivers/spi.h>
8 #include <zephyr/drivers/spi/rtio.h>
30 nrfx_spi_t spi; member
90 struct spi_nrfx_data *dev_data = dev->data; in configure()
91 const struct spi_nrfx_config *dev_config = dev->config; in configure()
92 struct spi_context *ctx = &dev_data->ctx; in configure()
96 if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) { in configure()
101 if (spi_cfg->operation & SPI_HALF_DUPLEX) { in configure()
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| D | spi_pw.c | 3 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/spi.h>
13 #include <zephyr/drivers/spi/rtio.h>
45 static bool is_spi_transfer_ongoing(struct spi_pw_data *spi) in is_spi_transfer_ongoing() argument
47 return spi_context_tx_on(&spi->ctx) || spi_context_rx_on(&spi->ctx); in is_spi_transfer_ongoing()
132 uint8_t dfs = SPI_WORD_SIZE_GET(config->operation); in spi_pw_get_frame_size()
137 LOG_WRN("Unsupported dfs, 1-byte size will be used"); in spi_pw_get_frame_size()
146 struct spi_pw_data *spi = dev->data; in spi_pw_cs_ctrl_enable() local
149 if (spi->cs_mode == CS_SW_MODE) { in spi_pw_cs_ctrl_enable()
151 } else if (spi->cs_mode == CS_GPIO_MODE) { in spi_pw_cs_ctrl_enable()
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| D | spi_mcux_ecspi.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi.h>
16 #include <zephyr/drivers/spi/rtio.h>
56 const struct spi_mcux_config *config = dev->config; in spi_mcux_transfer_next_packet()
57 struct spi_mcux_data *data = dev->data; in spi_mcux_transfer_next_packet()
58 ECSPI_Type *base = config->base; in spi_mcux_transfer_next_packet()
59 struct spi_context *ctx = &data->ctx; in spi_mcux_transfer_next_packet()
63 if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) { in spi_mcux_transfer_next_packet()
65 spi_context_cs_control(&data->ctx, false); in spi_mcux_transfer_next_packet()
66 spi_context_complete(&data->ctx, dev, 0); in spi_mcux_transfer_next_packet()
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| D | spi_rv32m1_lpspi.c | 6 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/spi.h>
13 #include <zephyr/drivers/spi/rtio.h>
49 const struct spi_mcux_config *config = dev->config; in spi_mcux_transfer_next_packet()
50 struct spi_mcux_data *data = dev->data; in spi_mcux_transfer_next_packet()
51 LPSPI_Type *base = config->base; in spi_mcux_transfer_next_packet()
52 struct spi_context *ctx = &data->ctx; in spi_mcux_transfer_next_packet()
56 if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) { in spi_mcux_transfer_next_packet()
58 spi_context_cs_control(&data->ctx, false); in spi_mcux_transfer_next_packet()
59 spi_context_complete(&data->ctx, dev, 0); in spi_mcux_transfer_next_packet()
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| D | spi_gecko_usart.c | 4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/drivers/spi.h>
17 #include <zephyr/drivers/spi/rtio.h>
46 : -1)
50 : -1)
55 : -1)
61 : -1)
68 : -1)
76 : -1)
120 const struct spi_gecko_config *gecko_config = dev->config; in spi_config()
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| D | spi_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include "spi.c"
21 #include <zephyr/drivers/spi.h>
22 #include <zephyr/drivers/spi/rtio.h>
32 /* SPI configuration structure */
38 #define SPI_CFG(dev) ((struct spi_b91_cfg *) ((dev)->config))
40 /* SPI data structure */
44 #define SPI_DATA(dev) ((struct spi_b91_data *) ((dev)->data))
55 pin = config->cs_pin[i]; in spi_b91_hw_cs_disable()
59 if (config->peripheral_id == PSPI_MODULE) { in spi_b91_hw_cs_disable()
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| /Zephyr-latest/drivers/wifi/infineon/ |
| D | airoc_whd_hal_spi.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/spi.h>
40 struct airoc_wifi_data *data = dev->data; in airoc_wifi_init_primary()
41 const struct airoc_wifi_config *config = dev->config; in airoc_wifi_init_primary()
49 .host_oob_pin = (void *)&config->wifi_host_wake_gpio, in airoc_wifi_init_primary()
57 data->prev_irq_state = 0; in airoc_wifi_init_primary()
61 gpio_pin_configure_dt(&config->bus_select_gpio, GPIO_OUTPUT_INACTIVE); in airoc_wifi_init_primary()
65 return -ENODEV; in airoc_wifi_init_primary()
68 if (!spi_is_ready_dt(&config->bus_dev.bus_spi)) { in airoc_wifi_init_primary()
69 LOG_ERR("SPI device is not ready"); in airoc_wifi_init_primary()
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