1 /*
2 * Copyright (c) 2018, NXP
3 *
4 * Forked off the spi_mcux_lpi2c driver.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define DT_DRV_COMPAT openisa_rv32m1_lpspi
10
11 #include <errno.h>
12 #include <zephyr/drivers/spi.h>
13 #include <zephyr/drivers/spi/rtio.h>
14 #include <zephyr/drivers/clock_control.h>
15 #include <fsl_lpspi.h>
16 #include <zephyr/drivers/pinctrl.h>
17
18 #define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
19 #include <zephyr/logging/log.h>
20 #include <zephyr/irq.h>
21 LOG_MODULE_REGISTER(spi_rv32m1_lpspi);
22
23 #include <soc.h>
24
25 #include "spi_context.h"
26
27 #define CHIP_SELECT_COUNT 4
28 #define MAX_DATA_WIDTH 4096
29
30 struct spi_mcux_config {
31 LPSPI_Type *base;
32 const struct device *clock_dev;
33 clock_control_subsys_t clock_subsys;
34 clock_ip_name_t clock_ip_name;
35 uint32_t clock_ip_src;
36 void (*irq_config_func)(const struct device *dev);
37 const struct pinctrl_dev_config *pincfg;
38 };
39
40 struct spi_mcux_data {
41 const struct device *dev;
42 lpspi_master_handle_t handle;
43 struct spi_context ctx;
44 size_t transfer_len;
45 };
46
spi_mcux_transfer_next_packet(const struct device * dev)47 static void spi_mcux_transfer_next_packet(const struct device *dev)
48 {
49 const struct spi_mcux_config *config = dev->config;
50 struct spi_mcux_data *data = dev->data;
51 LPSPI_Type *base = config->base;
52 struct spi_context *ctx = &data->ctx;
53 lpspi_transfer_t transfer;
54 status_t status;
55
56 if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) {
57 /* nothing left to rx or tx, we're done! */
58 spi_context_cs_control(&data->ctx, false);
59 spi_context_complete(&data->ctx, dev, 0);
60 return;
61 }
62
63 transfer.configFlags = kLPSPI_MasterPcsContinuous |
64 (ctx->config->slave << LPSPI_MASTER_PCS_SHIFT);
65
66 if (ctx->tx_len == 0) {
67 /* rx only, nothing to tx */
68 transfer.txData = NULL;
69 transfer.rxData = ctx->rx_buf;
70 transfer.dataSize = ctx->rx_len;
71 } else if (ctx->rx_len == 0) {
72 /* tx only, nothing to rx */
73 transfer.txData = (uint8_t *) ctx->tx_buf;
74 transfer.rxData = NULL;
75 transfer.dataSize = ctx->tx_len;
76 } else if (ctx->tx_len == ctx->rx_len) {
77 /* rx and tx are the same length */
78 transfer.txData = (uint8_t *) ctx->tx_buf;
79 transfer.rxData = ctx->rx_buf;
80 transfer.dataSize = ctx->tx_len;
81 } else if (ctx->tx_len > ctx->rx_len) {
82 /* Break up the tx into multiple transfers so we don't have to
83 * rx into a longer intermediate buffer. Leave chip select
84 * active between transfers.
85 */
86 transfer.txData = (uint8_t *) ctx->tx_buf;
87 transfer.rxData = ctx->rx_buf;
88 transfer.dataSize = ctx->rx_len;
89 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
90 } else {
91 /* Break up the rx into multiple transfers so we don't have to
92 * tx from a longer intermediate buffer. Leave chip select
93 * active between transfers.
94 */
95 transfer.txData = (uint8_t *) ctx->tx_buf;
96 transfer.rxData = ctx->rx_buf;
97 transfer.dataSize = ctx->tx_len;
98 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
99 }
100
101 if (!(ctx->tx_count <= 1 && ctx->rx_count <= 1)) {
102 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
103 }
104
105 data->transfer_len = transfer.dataSize;
106 status = LPSPI_MasterTransferNonBlocking(base, &data->handle,
107 &transfer);
108 if (status != kStatus_Success) {
109 LOG_ERR("Transfer could not start");
110 }
111 }
112
spi_mcux_isr(const struct device * dev)113 static void spi_mcux_isr(const struct device *dev)
114 {
115 const struct spi_mcux_config *config = dev->config;
116 struct spi_mcux_data *data = dev->data;
117 LPSPI_Type *base = config->base;
118
119 LPSPI_MasterTransferHandleIRQ(base, &data->handle);
120 }
121
spi_mcux_master_transfer_callback(LPSPI_Type * base,lpspi_master_handle_t * handle,status_t status,void * userData)122 static void spi_mcux_master_transfer_callback(LPSPI_Type *base,
123 lpspi_master_handle_t *handle,
124 status_t status, void *userData)
125 {
126 struct spi_mcux_data *data = userData;
127
128 spi_context_update_tx(&data->ctx, 1, data->transfer_len);
129 spi_context_update_rx(&data->ctx, 1, data->transfer_len);
130
131 spi_mcux_transfer_next_packet(data->dev);
132 }
133
spi_mcux_configure(const struct device * dev,const struct spi_config * spi_cfg)134 static int spi_mcux_configure(const struct device *dev,
135 const struct spi_config *spi_cfg)
136 {
137 const struct spi_mcux_config *config = dev->config;
138 struct spi_mcux_data *data = dev->data;
139 LPSPI_Type *base = config->base;
140 lpspi_master_config_t master_config;
141 uint32_t clock_freq;
142 uint32_t word_size;
143
144 if (spi_context_configured(&data->ctx, spi_cfg)) {
145 /* This configuration is already in use */
146 return 0;
147 }
148
149 if (spi_cfg->operation & SPI_HALF_DUPLEX) {
150 LOG_ERR("Half-duplex not supported");
151 return -ENOTSUP;
152 }
153
154 LPSPI_MasterGetDefaultConfig(&master_config);
155
156 if (spi_cfg->slave > CHIP_SELECT_COUNT) {
157 LOG_ERR("Slave %d is greater than %d",
158 spi_cfg->slave,
159 CHIP_SELECT_COUNT);
160 return -EINVAL;
161 }
162
163 word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
164 if (word_size > MAX_DATA_WIDTH) {
165 LOG_ERR("Word size %d is greater than %d",
166 word_size, MAX_DATA_WIDTH);
167 return -EINVAL;
168 }
169
170 master_config.bitsPerFrame = word_size;
171
172 master_config.cpol =
173 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
174 ? kLPSPI_ClockPolarityActiveLow
175 : kLPSPI_ClockPolarityActiveHigh;
176
177 master_config.cpha =
178 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
179 ? kLPSPI_ClockPhaseSecondEdge
180 : kLPSPI_ClockPhaseFirstEdge;
181
182 master_config.direction =
183 (spi_cfg->operation & SPI_TRANSFER_LSB)
184 ? kLPSPI_LsbFirst
185 : kLPSPI_MsbFirst;
186
187 master_config.baudRate = spi_cfg->frequency;
188
189 if (!device_is_ready(config->clock_dev)) {
190 LOG_ERR("clock control device not ready");
191 return -ENODEV;
192 }
193
194 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
195 &clock_freq)) {
196 return -EINVAL;
197 }
198
199 LPSPI_MasterInit(base, &master_config, clock_freq);
200
201 LPSPI_MasterTransferCreateHandle(base, &data->handle,
202 spi_mcux_master_transfer_callback,
203 data);
204
205 LPSPI_SetDummyData(base, 0);
206
207 data->ctx.config = spi_cfg;
208
209 return 0;
210 }
211
transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,bool asynchronous,spi_callback_t cb,void * userdata)212 static int transceive(const struct device *dev,
213 const struct spi_config *spi_cfg,
214 const struct spi_buf_set *tx_bufs,
215 const struct spi_buf_set *rx_bufs,
216 bool asynchronous,
217 spi_callback_t cb,
218 void *userdata)
219 {
220 struct spi_mcux_data *data = dev->data;
221 int ret;
222
223 spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
224
225 ret = spi_mcux_configure(dev, spi_cfg);
226 if (ret) {
227 goto out;
228 }
229
230 spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
231
232 spi_context_cs_control(&data->ctx, true);
233
234 spi_mcux_transfer_next_packet(dev);
235
236 ret = spi_context_wait_for_completion(&data->ctx);
237 out:
238 spi_context_release(&data->ctx, ret);
239
240 return ret;
241 }
242
spi_mcux_transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs)243 static int spi_mcux_transceive(const struct device *dev,
244 const struct spi_config *spi_cfg,
245 const struct spi_buf_set *tx_bufs,
246 const struct spi_buf_set *rx_bufs)
247 {
248 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
249 }
250
251 #ifdef CONFIG_SPI_ASYNC
spi_mcux_transceive_async(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,spi_callback_t cb,void * userdata)252 static int spi_mcux_transceive_async(const struct device *dev,
253 const struct spi_config *spi_cfg,
254 const struct spi_buf_set *tx_bufs,
255 const struct spi_buf_set *rx_bufs,
256 spi_callback_t cb,
257 void *userdata)
258 {
259 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
260 }
261 #endif /* CONFIG_SPI_ASYNC */
262
spi_mcux_release(const struct device * dev,const struct spi_config * spi_cfg)263 static int spi_mcux_release(const struct device *dev,
264 const struct spi_config *spi_cfg)
265 {
266 struct spi_mcux_data *data = dev->data;
267
268 spi_context_unlock_unconditionally(&data->ctx);
269
270 return 0;
271 }
272
spi_mcux_init(const struct device * dev)273 static int spi_mcux_init(const struct device *dev)
274 {
275 int err;
276 const struct spi_mcux_config *config = dev->config;
277 struct spi_mcux_data *data = dev->data;
278
279 CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
280
281 config->irq_config_func(dev);
282
283 data->dev = dev;
284
285 err = spi_context_cs_configure_all(&data->ctx);
286 if (err < 0) {
287 return err;
288 }
289
290 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
291 if (err != 0) {
292 return err;
293 }
294
295 spi_context_unlock_unconditionally(&data->ctx);
296
297 return 0;
298 }
299
300 static DEVICE_API(spi, spi_mcux_driver_api) = {
301 .transceive = spi_mcux_transceive,
302 #ifdef CONFIG_SPI_ASYNC
303 .transceive_async = spi_mcux_transceive_async,
304 #endif
305 #ifdef CONFIG_SPI_RTIO
306 .iodev_submit = spi_rtio_iodev_default_submit,
307 #endif
308 .release = spi_mcux_release,
309 };
310
311 #define SPI_RV32M1_INIT(n) \
312 PINCTRL_DT_INST_DEFINE(n); \
313 \
314 static void spi_mcux_config_func_##n(const struct device *dev); \
315 \
316 static const struct spi_mcux_config spi_mcux_config_##n = { \
317 .base = (LPSPI_Type *) DT_INST_REG_ADDR(n), \
318 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
319 .clock_subsys = (clock_control_subsys_t) \
320 DT_INST_CLOCKS_CELL(n, name), \
321 .irq_config_func = spi_mcux_config_func_##n, \
322 .clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
323 .clock_ip_src = kCLOCK_IpSrcFircAsync, \
324 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
325 }; \
326 \
327 static struct spi_mcux_data spi_mcux_data_##n = { \
328 SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx), \
329 SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx), \
330 SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
331 }; \
332 \
333 SPI_DEVICE_DT_INST_DEFINE(n, spi_mcux_init, NULL, \
334 &spi_mcux_data_##n, \
335 &spi_mcux_config_##n, \
336 POST_KERNEL, \
337 CONFIG_SPI_INIT_PRIORITY, \
338 &spi_mcux_driver_api); \
339 \
340 static void spi_mcux_config_func_##n(const struct device *dev) \
341 { \
342 IRQ_CONNECT(DT_INST_IRQN(n), \
343 0, \
344 spi_mcux_isr, DEVICE_DT_INST_GET(n), 0); \
345 irq_enable(DT_INST_IRQN(n)); \
346 }
347
348 DT_INST_FOREACH_STATUS_OKAY(SPI_RV32M1_INIT)
349
