1 /*
2 * Copyright (c) 2024, Basalte bv
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_ecspi
8
9 #include <zephyr/logging/log.h>
10 LOG_MODULE_REGISTER(spi_mcux_ecspi, CONFIG_SPI_LOG_LEVEL);
11
12 #include <zephyr/device.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/pinctrl.h>
15 #include <zephyr/drivers/spi.h>
16 #include <zephyr/drivers/spi/rtio.h>
17 #include <fsl_ecspi.h>
18
19 #include "spi_context.h"
20
21 #define SPI_MCUX_ECSPI_MAX_BURST 4096
22
23 struct spi_mcux_config {
24 ECSPI_Type *base;
25 const struct pinctrl_dev_config *pincfg;
26 const struct device *clock_dev;
27 clock_control_subsys_t clock_subsys;
28 void (*irq_config_func)(const struct device *dev);
29 };
30
31 struct spi_mcux_data {
32 ecspi_master_handle_t handle;
33 struct spi_context ctx;
34
35 uint16_t dfs;
36 uint16_t word_size;
37
38 uint32_t rx_data;
39 uint32_t tx_data;
40 };
41
bytes_per_word(uint16_t bits_per_word)42 static inline uint16_t bytes_per_word(uint16_t bits_per_word)
43 {
44 if (bits_per_word <= 8U) {
45 return 1U;
46 }
47 if (bits_per_word <= 16U) {
48 return 2U;
49 }
50
51 return 4U;
52 }
53
spi_mcux_transfer_next_packet(const struct device * dev)54 static void spi_mcux_transfer_next_packet(const struct device *dev)
55 {
56 const struct spi_mcux_config *config = dev->config;
57 struct spi_mcux_data *data = dev->data;
58 ECSPI_Type *base = config->base;
59 struct spi_context *ctx = &data->ctx;
60 ecspi_transfer_t transfer;
61 status_t status;
62
63 if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) {
64 /* nothing left to rx or tx, we're done! */
65 spi_context_cs_control(&data->ctx, false);
66 spi_context_complete(&data->ctx, dev, 0);
67 return;
68 }
69
70 transfer.channel = ctx->config->slave;
71
72 if (spi_context_rx_buf_on(ctx)) {
73 transfer.rxData = &data->rx_data;
74 } else {
75 transfer.rxData = NULL;
76 }
77
78 if (spi_context_tx_buf_on(ctx)) {
79 switch (data->dfs) {
80 case 1U:
81 data->tx_data = UNALIGNED_GET((uint8_t *)ctx->tx_buf);
82 break;
83 case 2U:
84 data->tx_data = UNALIGNED_GET((uint16_t *)ctx->tx_buf);
85 break;
86 case 4U:
87 data->tx_data = UNALIGNED_GET((uint32_t *)ctx->tx_buf);
88 break;
89 }
90
91 transfer.txData = &data->tx_data;
92 } else {
93 transfer.txData = NULL;
94 }
95
96 transfer.dataSize = data->dfs;
97
98 status = ECSPI_MasterTransferNonBlocking(base, &data->handle, &transfer);
99 if (status != kStatus_Success) {
100 LOG_ERR("Transfer could not start");
101 spi_context_cs_control(&data->ctx, false);
102 spi_context_complete(&data->ctx, dev, -EIO);
103 }
104 }
105
spi_mcux_isr(const struct device * dev)106 static void spi_mcux_isr(const struct device *dev)
107 {
108 const struct spi_mcux_config *config = dev->config;
109 struct spi_mcux_data *data = dev->data;
110 ECSPI_Type *base = config->base;
111
112 ECSPI_MasterTransferHandleIRQ(base, &data->handle);
113 }
114
spi_mcux_master_transfer_callback(ECSPI_Type * base,ecspi_master_handle_t * handle,status_t status,void * user_data)115 static void spi_mcux_master_transfer_callback(ECSPI_Type *base, ecspi_master_handle_t *handle,
116 status_t status, void *user_data)
117 {
118 const struct device *dev = (const struct device *)user_data;
119 struct spi_mcux_data *data = dev->data;
120
121 if (spi_context_rx_buf_on(&data->ctx)) {
122 switch (data->dfs) {
123 case 1:
124 UNALIGNED_PUT(data->rx_data, (uint8_t *)data->ctx.rx_buf);
125 break;
126 case 2:
127 UNALIGNED_PUT(data->rx_data, (uint16_t *)data->ctx.rx_buf);
128 break;
129 case 4:
130 UNALIGNED_PUT(data->rx_data, (uint32_t *)data->ctx.rx_buf);
131 break;
132 }
133 }
134
135 spi_context_update_tx(&data->ctx, data->dfs, 1);
136 spi_context_update_rx(&data->ctx, data->dfs, 1);
137
138 spi_mcux_transfer_next_packet(dev);
139 }
140
spi_mcux_configure(const struct device * dev,const struct spi_config * spi_cfg)141 static int spi_mcux_configure(const struct device *dev,
142 const struct spi_config *spi_cfg)
143 {
144 const struct spi_mcux_config *config = dev->config;
145 struct spi_mcux_data *data = dev->data;
146 ECSPI_Type *base = config->base;
147 ecspi_master_config_t master_config;
148 uint32_t clock_freq;
149 uint16_t word_size;
150
151 if (spi_context_configured(&data->ctx, spi_cfg)) {
152 /* This configuration is already in use */
153 return 0;
154 }
155
156 if (spi_cfg->operation & SPI_HALF_DUPLEX) {
157 LOG_ERR("Half-duplex not supported");
158 return -ENOTSUP;
159 }
160
161 if (spi_cfg->operation & SPI_TRANSFER_LSB) {
162 LOG_ERR("HW byte re-ordering not supported");
163 return -ENOTSUP;
164 }
165
166 if (spi_cfg->slave > kECSPI_Channel3) {
167 LOG_ERR("Slave %d is greater than %d", spi_cfg->slave, kECSPI_Channel3);
168 return -EINVAL;
169 }
170
171 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq)) {
172 LOG_ERR("Failed to get clock rate");
173 return -EINVAL;
174 }
175
176 word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
177 if (0 == word_size || word_size > 32) {
178 LOG_ERR("Invalid word size (0 < %d <= 32)", word_size);
179 return -EINVAL;
180 }
181
182 ECSPI_MasterGetDefaultConfig(&master_config);
183
184 master_config.channel = (ecspi_channel_source_t)spi_cfg->slave;
185 master_config.channelConfig.polarity =
186 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
187 ? kECSPI_PolarityActiveLow
188 : kECSPI_PolarityActiveHigh;
189 master_config.channelConfig.phase =
190 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
191 ? kECSPI_ClockPhaseSecondEdge
192 : kECSPI_ClockPhaseFirstEdge;
193 master_config.baudRate_Bps = spi_cfg->frequency;
194 master_config.burstLength = word_size;
195
196 master_config.enableLoopback = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_LOOP);
197
198 if (!spi_cs_is_gpio(spi_cfg)) {
199 uint32_t clock_cycles =
200 DIV_ROUND_UP(spi_cfg->cs.delay * USEC_PER_SEC, spi_cfg->frequency);
201
202 if (clock_cycles > 63U) {
203 LOG_ERR("CS delay is greater than 63 clock cycles (%u)", clock_cycles);
204 return -EINVAL;
205 }
206 master_config.chipSelectDelay = (uint8_t)clock_cycles;
207 }
208
209 ECSPI_MasterInit(base, &master_config, clock_freq);
210 ECSPI_MasterTransferCreateHandle(base, &data->handle,
211 spi_mcux_master_transfer_callback,
212 (void *)dev);
213
214 data->word_size = word_size;
215 data->dfs = bytes_per_word(word_size);
216 data->ctx.config = spi_cfg;
217
218 return 0;
219 }
220
transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,bool asynchronous,spi_callback_t cb,void * userdata)221 static int transceive(const struct device *dev,
222 const struct spi_config *spi_cfg,
223 const struct spi_buf_set *tx_bufs,
224 const struct spi_buf_set *rx_bufs,
225 bool asynchronous,
226 spi_callback_t cb,
227 void *userdata)
228 {
229 struct spi_mcux_data *data = dev->data;
230 int ret;
231
232 spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
233
234 ret = spi_mcux_configure(dev, spi_cfg);
235 if (ret) {
236 goto out;
237 }
238
239 spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, data->dfs);
240 spi_context_cs_control(&data->ctx, true);
241
242 spi_mcux_transfer_next_packet(dev);
243 ret = spi_context_wait_for_completion(&data->ctx);
244
245 out:
246 spi_context_release(&data->ctx, ret);
247
248 return ret;
249 }
250
spi_mcux_transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs)251 static int spi_mcux_transceive(const struct device *dev,
252 const struct spi_config *spi_cfg,
253 const struct spi_buf_set *tx_bufs,
254 const struct spi_buf_set *rx_bufs)
255 {
256 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
257 }
258
259 #ifdef CONFIG_SPI_ASYNC
spi_mcux_transceive_async(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,spi_callback_t cb,void * userdata)260 static int spi_mcux_transceive_async(const struct device *dev,
261 const struct spi_config *spi_cfg,
262 const struct spi_buf_set *tx_bufs,
263 const struct spi_buf_set *rx_bufs,
264 spi_callback_t cb,
265 void *userdata)
266 {
267 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
268 }
269 #endif /* CONFIG_SPI_ASYNC */
270
spi_mcux_release(const struct device * dev,const struct spi_config * spi_cfg)271 static int spi_mcux_release(const struct device *dev, const struct spi_config *spi_cfg)
272 {
273 struct spi_mcux_data *data = dev->data;
274
275 ARG_UNUSED(spi_cfg);
276
277 spi_context_unlock_unconditionally(&data->ctx);
278
279 return 0;
280 }
281
spi_mcux_init(const struct device * dev)282 static int spi_mcux_init(const struct device *dev)
283 {
284 int ret;
285 const struct spi_mcux_config *config = dev->config;
286 struct spi_mcux_data *data = dev->data;
287
288 config->irq_config_func(dev);
289
290 ret = spi_context_cs_configure_all(&data->ctx);
291 if (ret < 0) {
292 return ret;
293 }
294
295 ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
296 if (ret < 0) {
297 return ret;
298 }
299
300 spi_context_unlock_unconditionally(&data->ctx);
301
302 return 0;
303 }
304
305 static DEVICE_API(spi, spi_mcux_driver_api) = {
306 .transceive = spi_mcux_transceive,
307 #ifdef CONFIG_SPI_ASYNC
308 .transceive_async = spi_mcux_transceive_async,
309 #endif
310 #ifdef CONFIG_SPI_RTIO
311 .iodev_submit = spi_rtio_iodev_default_submit,
312 #endif
313 .release = spi_mcux_release,
314 };
315
316 #define SPI_MCUX_ECSPI_INIT(n) \
317 PINCTRL_DT_INST_DEFINE(n); \
318 static void spi_mcux_config_func_##n(const struct device *dev); \
319 \
320 static const struct spi_mcux_config spi_mcux_config_##n = { \
321 .base = (ECSPI_Type *) DT_INST_REG_ADDR(n), \
322 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
323 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
324 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
325 .irq_config_func = spi_mcux_config_func_##n, \
326 }; \
327 \
328 static struct spi_mcux_data spi_mcux_data_##n = { \
329 SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx), \
330 SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx), \
331 SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
332 }; \
333 \
334 SPI_DEVICE_DT_INST_DEFINE(n, spi_mcux_init, NULL, \
335 &spi_mcux_data_##n, &spi_mcux_config_##n, \
336 POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
337 &spi_mcux_driver_api); \
338 \
339 static void spi_mcux_config_func_##n(const struct device *dev) \
340 { \
341 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
342 spi_mcux_isr, DEVICE_DT_INST_GET(n), 0); \
343 \
344 irq_enable(DT_INST_IRQN(n)); \
345 }
346
347 DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_ECSPI_INIT)
348
