Searched full:snvs (Results 1 – 15 of 15) sorted by relevance
1 # MCUXpresso SDK SNVS (Secure) RTC7 bool "IMX SNVS RTC driver"11 Enable support for the IMX SNVS High/Low Power clock.14 bool "IMX SNVS SRTC low power support"18 Enable the low power SRTC in SNVS to synchronise.21 bool "IMX SNVS wake-up on SRTC alarm"
312 "unsupported snvs instance");
7 description: NXP SNVS LP/HP RTC9 compatible: "nxp,imx-snvs-rtc"
9 * @brief Real-time clock control based on the MCUX IMX SNVS counter API.35 * @param dev the IMX SNVS RTC device pointer.
3 # Enable the SNVS RTC
40 powered back on. Alternatively, wait 10 seconds for the SNVS RTC
11 drivers.counter.mcux.snvs.rtc:
39 * pue_pus_snvs: in SNVS domain, shifted ode field105 uint8_t snvs_mux: 1; /* Is pinmux reg SNVS type */
72 pin-snvs:
81 /* Enable the SNVS RTC as a wakeup source from soft-off mode, in case an RTC alarm in lpm_enter_soft_off_mode()85 SNVS->LPCR |= SNVS_LPCR_TOP_MASK; in lpm_enter_soft_off_mode()
37 * pue_pus_snvs: in SNVS domain, shifted ode field
125 /* PDRV/SNVS/LPSR type register layout */ in mcux_igpio_configure()137 /* PDRV/SNVS/LPSR reg have different ODE bits */ in mcux_igpio_configure()
180 Set if the SNVS module is present on the SoC.
312 snvs: snvs@400d4000 { label313 compatible = "nxp,imx-snvs";317 compatible = "nxp,imx-snvs-rtc";
254 * NXP i.MX RT11xx series SNVS pin control name identifiers have been updated to
