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/Zephyr-latest/drivers/clock_control/
DKconfig.mcux_scg1 # MCUXpresso SDK SCG
8 bool "MCUX SCG driver"
12 Enable support for mcux scg driver.
15 bool "MCUX driver for K4 Generation SCG"
19 Enable support for SCG K4 driver
Dclock_control_mcux_scg.c140 #error Unsupported SCG clkout clock source in mcux_scg_init()
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c36 "Invalid SCG slow clock divider value");
38 "Invalid SCG bus clock divider value");
42 "Invalid SCG core clock divider value");
45 "Invalid SCG core clock divider value");
60 #error Invalid SCG core clock source
67 "Invalid SCG SOSC divider 1 value");
69 "Invalid SCG SOSC divider 2 value");
82 "Invalid SCG SIRC divider 1 value");
84 "Invalid SCG SIRC divider 2 value");
94 #error Invalid SCG SIRC clock frequency
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_mcxw71.dtsi144 scg: clock-controller@1e000 { label
145 compatible = "nxp,scg-k4";
153 clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
159 clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
165 clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
171 clocks = <&scg SCG_K4_SLOW_CLK 0>;
178 clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
186 clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
197 clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
208 clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
[all …]
Dnxp_ke17z512.dtsi52 clocks = <&scg KINETIS_SCG_BUS_CLK>;
61 clocks = <&scg KINETIS_SCG_BUS_CLK>;
Dnxp_ke1xf.dtsi127 scg: scg@40064000 { label
128 compatible = "nxp,kinetis-scg";
280 clocks = <&scg KINETIS_SCG_BUS_CLK>;
310 clocks = <&scg KINETIS_SCG_BUS_CLK>;
408 clocks = <&scg KINETIS_SCG_BUS_CLK>;
419 clocks = <&scg KINETIS_SCG_BUS_CLK>;
577 clocks = <&scg KINETIS_SCG_BUS_CLK>;
585 clocks = <&scg KINETIS_SCG_BUS_CLK>;
593 clocks = <&scg KINETIS_SCG_BUS_CLK>;
Dnxp_ke1xz.dtsi74 scg: scg@40064000 { label
76 compatible = "nxp,kinetis-scg";
378 clocks = <&scg KINETIS_SCG_BUS_CLK>;
420 clocks = <&scg KINETIS_SCG_BUS_CLK>;
/Zephyr-latest/dts/bindings/clock/
Dnxp,scg-k4.yaml4 description: NXP K4 Generation SCG (System Clock Generator) IP node
6 compatible: "nxp,scg-k4"
Dnxp,kinetis-scg.yaml4 description: NXP Kinetis SCG (System Clock Generator) IP node
6 compatible: "nxp,kinetis-scg"
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dkinetis_scg.h10 /* SCG system oscillator mode */
15 /* SCG clock controller clock names */
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c35 "Invalid SCG bus clock divider value");
37 "Invalid SCG core clock divider value");
51 "Invalid SCG SIRC divider 2 value");
60 #error Invalid SCG SIRC clock frequency
66 "Invalid SCG FIRC divider 2 value");
79 #error Invalid SCG FIRC clock frequency
/Zephyr-latest/tests/drivers/pwm/pwm_loopback/boards/
Dfrdm_ke17z.overlay41 clocks = <&scg KINETIS_SCG_SIRC_CLK>;
56 &scg {
Dfrdm_ke17z512.overlay41 clocks = <&scg KINETIS_SCG_SIRC_CLK>;
56 &scg {
/Zephyr-latest/drivers/timer/
Drv32m1_lptmr_timer.c81 if ((SCG->SIRCCSR & SCG_SIRCCSR_SIRCEN_MASK) == SCG_SIRCCSR_SIRCEN(0)) { in sys_clock_driver_init()
104 sircdiv = SCG->SIRCDIV; in sys_clock_driver_init()
107 SCG->SIRCDIV = sircdiv; in sys_clock_driver_init()
135 if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) != SIRC_RANGE_8MHZ) { in sys_clock_driver_init()
/Zephyr-latest/dts/bindings/can/
Dnxp,flexcan.yaml14 clocks = <&scg KINETIS_SCG_BUS_CLK>;
/Zephyr-latest/boards/nxp/frdm_ke17z512/
Dfrdm_ke17z512.dts117 &scg {
148 clocks = <&scg KINETIS_SCG_SIRC_CLK>;
/Zephyr-latest/dts/bindings/comparator/
Dnxp,kinetis-acmp.yaml14 clocks = <&scg KINETIS_SCG_BUS_CLK>;
/Zephyr-latest/boards/nxp/frdm_ke17z/
Dfrdm_ke17z.dts131 clocks = <&scg KINETIS_SCG_SIRC_CLK>;
/Zephyr-latest/modules/
DKconfig.mcux207 Set if the system clock generator (SCG) module is present in the
/Zephyr-latest/boards/nxp/frdm_mcxn236/
Dboard.c66 /* Enable SCG clock */ in frdm_mcxn236_init()
/Zephyr-latest/boards/nxp/twr_ke18f/
Dtwr_ke18f.dts157 &scg {
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c91 /* Enable SCG clock */ in frdm_mcxn947_init()
/Zephyr-latest/doc/releases/
Drelease-notes-2.0.rst196 * Added NXP Kinetis MCG, SCG, and PCC drivers