| /Zephyr-latest/dts/riscv/qemu/ |
| D | virt-riscv32.dtsi | 9 #include <qemu/virt-riscv.dtsi>
14 riscv,isa = "rv32gc";
18 riscv,isa = "rv32gc";
22 riscv,isa = "rv32gc";
26 riscv,isa = "rv32gc";
30 riscv,isa = "rv32gc";
34 riscv,isa = "rv32gc";
38 riscv,isa = "rv32gc";
42 riscv,isa = "rv32gc";
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| D | virt-riscv64.dtsi | 9 #include <qemu/virt-riscv.dtsi>
14 riscv,isa = "rv64gc";
18 riscv,isa = "rv64gc";
22 riscv,isa = "rv64gc";
26 riscv,isa = "rv64gc";
30 riscv,isa = "rv64gc";
34 riscv,isa = "rv64gc";
38 riscv,isa = "rv64gc";
42 riscv,isa = "rv64gc";
|
| D | virt-riscv.dtsi | 18 compatible = "riscv-virtio";
19 model = "riscv-virtio,qemu";
44 compatible = "qemu,riscv-virt", "riscv";
47 compatible = "riscv,cpu-intc";
58 compatible = "qemu,riscv-virt", "riscv";
61 compatible = "riscv,cpu-intc";
72 compatible = "qemu,riscv-virt", "riscv";
75 compatible = "riscv,cpu-intc";
86 compatible = "qemu,riscv-virt", "riscv";
89 compatible = "riscv,cpu-intc";
[all …]
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| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv64-fu740.dtsi | 35 compatible = "sifive,s7", "riscv";
38 riscv,isa = "rv64imac_zicsr_zifencei";
42 compatible = "riscv,cpu-intc";
49 compatible = "sifive,u74", "riscv";
51 mmu-type = "riscv,sv39";
53 riscv,isa = "rv64gc";
56 compatible = "riscv,cpu-intc";
63 compatible = "sifive,u74", "riscv";
65 mmu-type = "riscv,sv39";
67 riscv,isa = "rv64gc";
[all …]
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| D | riscv64-fu540.dtsi | 36 compatible = "sifive,e51", "riscv";
40 riscv,isa = "rv64imac_zicsr_zifencei";
42 compatible = "riscv,cpu-intc";
50 compatible = "sifive,u54", "riscv";
52 mmu-type = "riscv,sv39";
56 riscv,isa = "rv64gc";
58 compatible = "riscv,cpu-intc";
67 compatible = "sifive,u54", "riscv";
69 mmu-type = "riscv,sv39";
73 riscv,isa = "rv64gc";
[all …]
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| /Zephyr-latest/dts/riscv/andes/ |
| D | andes_v5_ae350.dtsi | 19 compatible = "andestech,andescore-v5", "riscv";
23 riscv,isa = "rv32gc_xandes";
24 mmu-type = "riscv,sv32";
29 compatible = "riscv,cpu-intc";
36 compatible = "andestech,andescore-v5", "riscv";
40 riscv,isa = "rv32gc_xandes";
41 mmu-type = "riscv,sv32";
46 compatible = "riscv,cpu-intc";
53 compatible = "andestech,andescore-v5", "riscv";
57 riscv,isa = "rv32gc_xandes";
[all …]
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| /Zephyr-latest/dts/bindings/cpu/ |
| D | riscv,cpus.yaml | 11 - riscv,sv32
12 - riscv,sv39
13 - riscv,sv48
14 - riscv,none
16 riscv,isa:
|
| D | ite,riscv-ite.yaml | 6 compatible: "ite,riscv-ite"
8 include: riscv,cpus.yaml
|
| /Zephyr-latest/dts/riscv/starfive/ |
| D | jh7110-visionfive-v2.dtsi | 23 compatible = "sifive,s7", "riscv";
26 riscv,isa = "rv64imac_zicsr_zifencei";
29 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u74", "riscv";
48 mmu-type = "riscv,sv39";
51 riscv,isa = "rv64imafdcg";
54 compatible = "riscv,cpu-intc";
61 compatible = "sifive,u74", "riscv";
73 mmu-type = "riscv,sv39";
76 riscv,isa = "rv64imafdcg";
[all …]
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| D | starfive_jh7100_beagle_v.dtsi | 22 compatible = "starfive,rocket0", "riscv";
34 mmu-type = "riscv,sv39";
37 riscv,isa = "rv64gc";
42 compatible = "riscv,cpu-intc";
51 compatible = "starfive,rocket0", "riscv";
63 mmu-type = "riscv,sv39";
66 riscv,isa = "rv64gc";
71 compatible = "riscv,cpu-intc";
132 riscv,max-priority = <7>;
133 riscv,ndev = <127>;
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| /Zephyr-latest/boards/sifive/hifive_unleashed/support/ |
| D | openocd_hifive_unleashed.cfg | 10 set _CHIPNAME riscv
14 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
15 target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
16 target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
17 target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
18 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
|
| /Zephyr-latest/boards/sifive/hifive_unmatched/support/ |
| D | openocd_hifive_unmatched.cfg | 10 set _CHIPNAME riscv
14 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
15 target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
16 target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
17 target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
18 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
|
| /Zephyr-latest/include/zephyr/arch/riscv/ |
| D | error.h | 9 * @brief RISCV public error handling
11 * RISCV-specific kernel error handling interface. Included by riscv/arch.h.
17 #include <zephyr/arch/riscv/syscall.h>
18 #include <zephyr/arch/riscv/exception.h>
|
| D | arch.h | 10 * @brief RISCV specific kernel interface header
11 * This header contains the RISCV specific kernel interface. It is
18 #include <zephyr/arch/riscv/thread.h>
19 #include <zephyr/arch/riscv/exception.h>
20 #include <zephyr/arch/riscv/irq.h>
21 #include <zephyr/arch/riscv/sys_io.h>
25 #include <zephyr/arch/riscv/syscall.h>
30 #include <zephyr/arch/riscv/csr.h>
31 #include <zephyr/arch/riscv/exception.h>
33 /* stacks, for RISCV architecture stack should be 16byte-aligned */
[all …]
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| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 4 description: SiFive RISCV-V platform-local interrupt controller
8 include: riscv,plic0.yaml
11 riscv,ndev:
|
| /Zephyr-latest/dts/riscv/microchip/ |
| D | mpfs.dtsi | 19 compatible = "sifive,e51", "riscv";
22 riscv,isa = "rv64imac_zicsr_zifencei";
24 compatible = "riscv,cpu-intc";
33 compatible = "sifive,u54", "riscv";
36 riscv,isa = "rv64gc";
38 compatible = "riscv,cpu-intc";
47 compatible = "sifive,u54", "riscv";
50 riscv,isa = "rv64gc";
52 compatible = "riscv,cpu-intc";
61 compatible = "sifive,u54", "riscv";
[all …]
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| D | microchip-miv.dtsi | 16 compatible = "microchip,miv", "riscv";
19 riscv,isa = "rv32ima_zicsr_zifencei";
21 compatible = "riscv,cpu-intc";
58 riscv,max-priority = <1>;
59 riscv,ndev = <31>;
|
| /Zephyr-latest/dts/riscv/ |
| D | renode_riscv32_virt.dtsi | 18 compatible = "renode,virt", "riscv";
21 riscv,isa = "rv32imac_zicsr_zifencei";
23 compatible = "riscv,cpu-intc";
60 riscv,max-priority = <1>;
61 riscv,ndev = <1023>;
71 riscv,max-priority = <1>;
72 riscv,ndev = <1023>;
|
| /Zephyr-latest/soc/common/riscv-privileged/ |
| D | soc_irq.S | 8 * common interrupt management code for riscv SOCs supporting the riscv
15 #include <zephyr/arch/riscv/irq.h>
19 * SOCs that do not truly follow the riscv privilege specification.
|
| /Zephyr-latest/soc/litex/litex_vexriscv/ |
| D | CMakeLists.txt | 8 ${ZEPHYR_BASE}/soc/common/riscv-privileged/soc_irq.S
9 ${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S
16 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
|
| /Zephyr-latest/arch/common/ |
| D | Kconfig | 8 depends on ARM || ARM64 || RISCV
15 https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
|
| /Zephyr-latest/tests/subsys/llext/ |
| D | testcase.yaml | 37 - riscv
54 - riscv
65 - riscv
77 - riscv
98 - riscv
111 - riscv
|
| /Zephyr-latest/tests/arch/riscv/atomic/ |
| D | testcase.yaml | 2 arch.riscv.atomic:
3 arch_allow: riscv
|
| /Zephyr-latest/tests/arch/riscv/fpu_sharing/ |
| D | testcase.yaml | 2 arch.riscv.fpu_sharing:
3 arch_allow: riscv
|
| /Zephyr-latest/boards/efinix/titanium_ti60_f225/ |
| D | titanium_ti60_f225.yaml | 2 name: titanium_ti60_f225 FPGA development kit with Efinix Sapphire riscv SoC
4 arch: riscv
|
