Lines Matching full:riscv
19 compatible = "andestech,andescore-v5", "riscv";
23 riscv,isa = "rv32gc_xandes";
24 mmu-type = "riscv,sv32";
29 compatible = "riscv,cpu-intc";
36 compatible = "andestech,andescore-v5", "riscv";
40 riscv,isa = "rv32gc_xandes";
41 mmu-type = "riscv,sv32";
46 compatible = "riscv,cpu-intc";
53 compatible = "andestech,andescore-v5", "riscv";
57 riscv,isa = "rv32gc_xandes";
58 mmu-type = "riscv,sv32";
63 compatible = "riscv,cpu-intc";
70 compatible = "andestech,andescore-v5", "riscv";
74 riscv,isa = "rv32gc_xandes";
75 mmu-type = "riscv,sv32";
80 compatible = "riscv,cpu-intc";
87 compatible = "andestech,andescore-v5", "riscv";
91 riscv,isa = "rv32gc_xandes";
92 mmu-type = "riscv,sv32";
97 compatible = "riscv,cpu-intc";
104 compatible = "andestech,andescore-v5", "riscv";
108 riscv,isa = "rv32gc_xandes";
109 mmu-type = "riscv,sv32";
114 compatible = "riscv,cpu-intc";
121 compatible = "andestech,andescore-v5", "riscv";
125 riscv,isa = "rv32gc_xandes";
126 mmu-type = "riscv,sv32";
131 compatible = "riscv,cpu-intc";
138 compatible = "andestech,andescore-v5", "riscv";
142 riscv,isa = "rv32gc_xandes";
143 mmu-type = "riscv,sv32";
148 compatible = "riscv,cpu-intc";
174 riscv,max-priority = <255>;
175 riscv,ndev = <1023>;
188 riscv,max-priority = <255>;
189 riscv,ndev = <1023>;