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/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr/src/
Dmain.c13 const struct mem_attr_region_t *region; in ZTEST() local
16 num_regions = mem_attr_get_regions(&region); in ZTEST()
23 if (region[idx].dt_size == 0x1000) { in ZTEST()
24 zassert_equal(region[idx].dt_addr, 0x10000000, "Wrong region address"); in ZTEST()
25 zassert_equal(region[idx].dt_size, 0x1000, "Wrong region size"); in ZTEST()
26 zassert_equal(region[idx].dt_attr, DT_MEM_ARM_MPU_FLASH | in ZTEST()
28 "Wrong region address"); in ZTEST()
29 zassert_str_equal(region[idx].dt_name, in ZTEST()
32 zassert_equal(region[idx].dt_addr, 0x20000000, "Wrong region address"); in ZTEST()
33 zassert_equal(region[idx].dt_size, 0x2000, "Wrong region size"); in ZTEST()
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/Zephyr-latest/tests/lib/devicetree/memory_region_flags/
Dapp.overlay11 compatible = "zephyr,memory-region";
13 zephyr,memory-region = "TEST_REGION_R";
14 zephyr,memory-region-flags = "r";
18 compatible = "zephyr,memory-region";
20 zephyr,memory-region = "TEST_REGION_NRWXAIL";
21 zephyr,memory-region-flags = "!rwxail";
25 compatible = "zephyr,memory-region";
27 zephyr,memory-region = "TEST_REGION_NO_FLAGS";
31 compatible = "zephyr,memory-region";
33 zephyr,memory-region = "TEST_REGION_NONE";
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/Zephyr-latest/soc/nordic/common/
Ddmm.c46 const struct dmm_region *region; member
57 static struct dmm_heap *dmm_heap_find(void *region) in dmm_heap_find() argument
63 if (dh->region->dt_addr == (uintptr_t)region) { in dmm_heap_find()
71 static bool is_region_cacheable(const struct dmm_region *region) in is_region_cacheable() argument
73 return (IS_ENABLED(CONFIG_DCACHE) && (region->dt_attr & DT_MEM_CACHEABLE)); in is_region_cacheable()
83 const struct dmm_region *region) in is_user_buffer_correctly_preallocated() argument
87 if (!is_buffer_within_region(addr, user_length, region->dt_addr, region->dt_size)) { in is_user_buffer_correctly_preallocated()
91 if (!is_region_cacheable(region)) { in is_user_buffer_correctly_preallocated()
92 /* Buffer is contained within non-cacheable region - use it as it is. */ in is_user_buffer_correctly_preallocated()
96 if (IS_ALIGNED(addr, region->dt_align)) { in is_user_buffer_correctly_preallocated()
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Ddmm.h28 /* Determine if memory region is cacheable. */
34 /* Determine required alignment of the data buffers in specified memory region.
35 * Cache line alignment is required if region is cacheable and data cache is enabled.
47 /* Determine required alignment of the data buffers in memory region
53 * @brief Get reference to memory region associated with the specified device node
57 * @return Reference to memory region. NULL if not defined for given device node.
64 * @brief Preallocate buffer in memory region associated with the specified device node
80 * Allocate an output buffer in memory region that given device can perform DMA transfers from.
95 * @param region Memory region associated with device to prepare the buffer for.
105 int dmm_buffer_out_prepare(void *region, void const *user_buffer, size_t user_length,
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/Zephyr-latest/tests/lib/shared_multi_heap/src/
Dmain.c22 struct shared_multi_heap_region region; member
28 .region = { \
41 static void smh_reg_map(struct shared_multi_heap_region *region) in smh_reg_map() argument
46 mem_attr = (region->attr == SMH_REG_ATTR_CACHEABLE) ? K_MEM_CACHE_WB : K_MEM_CACHE_NONE; in smh_reg_map()
49 k_mem_map_phys_bare(&v_addr, region->addr, region->size, mem_attr); in smh_reg_map()
51 region->addr = (uintptr_t) v_addr; in smh_reg_map()
56 * Given a virtual address retrieve the original memory region that the mapping
62 if ((uintptr_t) v_addr >= map[reg].region.addr && in get_region_map()
63 (uintptr_t) v_addr < map[reg].region.addr + map[reg].region.size) { in get_region_map()
108 if (reg_map->region.attr == DT_MEM_ARM_MPU_UNKNOWN) { in fill_multi_heap()
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/Zephyr-latest/modules/loramac-node/
DCMakeLists.txt32 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region
63 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/Region.c
64 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionCommon.c
67 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionEU868.c
70 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionBaseUS.c
71 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionUS915.c
74 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionCN779.c
77 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionEU433.c
80 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionBaseUS.c
81 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionAU915.c
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/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/src/
Dmain.c21 const struct mem_attr_region_t *region; in ZTEST() local
45 * memory region. in ZTEST()
47 region = mem_attr_heap_get_region(block); in ZTEST()
48 zassert_equal(region->dt_addr, ADDR_MEM_CACHE_SW, in ZTEST()
49 "Memory allocated from the wrong region"); in ZTEST()
59 * memory region. in ZTEST()
61 region = mem_attr_heap_get_region(block); in ZTEST()
62 zassert_equal(region->dt_addr, ADDR_MEM_NON_CACHE_SW, in ZTEST()
63 "Memory allocated from the wrong region"); in ZTEST()
73 * memory region. in ZTEST()
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/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/boards/
Dqemu_cortex_m3.overlay7 compatible = "zephyr,memory-region", "mmio-sram";
9 zephyr,memory-region = "MEM_CACHEABLE";
14 compatible = "zephyr,memory-region", "mmio-sram";
16 zephyr,memory-region = "MEM_CACHEABLE_SW";
21 compatible = "zephyr,memory-region", "mmio-sram";
23 zephyr,memory-region = "MEM_NON_CACHEABLE_SW";
28 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "MEM_DMA_SW";
35 compatible = "zephyr,memory-region", "mmio-sram";
37 zephyr,memory-region = "MEM_CACHEABLE_SW_BIG";
[all …]
/Zephyr-latest/include/zephyr/linker/
Ddevicetree_regions.h18 * @brief Get the linker memory-region name in a token form
20 * This attempts to use the zephyr,memory-region property (with
29 * zephyr,memory-region = "MY_NAME";
32 * zephyr,memory-region = "MY@OTHER@NAME";
46 * @return the name of the memory memory region the node will generate
52 * @brief Get the linker memory-region name
54 * This attempts to use the zephyr,memory-region property (with
63 * zephyr,memory-region = "MY_NAME";
66 * zephyr,memory-region = "MY@OTHER@NAME";
80 * @return the name of the memory memory region the node will generate
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Dlinker-devnull.h41 /* Determine where to put the devnull region. It should be adjacent to the ROM
42 * region. If ROM starts after RAM or the distance between ROM and RAM is big
43 * enough to fit the devnull region then devnull region is placed just after
44 * the ROM region. If it cannot be done then the devnull region is placed before
45 * the ROM region. It is possible that the devnull region cannot be placed
47 * case compilation fails and the devnull region is not supported in that
66 #error "Cannot place devnull segment adjacent to ROM region."
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v4_internal.h15 /* For MPU version 4, the minimum protection region size is 32 bytes */
21 /* ARC MPU version 4 does not support mpu region overlap in hardware
22 * so if we want to allocate MPU region dynamically, e.g. thread stack,
23 * memory domain from a background region, a dynamic region splitting
27 * As a trade off, we can use the default mpu region as the background region
28 * to avoid the dynamic region splitting. This will give more privilege to
29 * codes in kernel mode which can access the memory region not covered by
32 * thread switch performance through default mpu region.
65 * Global array, holding the MPU region index of
66 * the memory region inside which dynamic memory
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/Zephyr-latest/soc/nxp/kinetis/k8x/
Dnxp_mpu_regions.c10 /* Region 0 */
17 * MPU, which means that if one region grants access then another
18 * region cannot revoke access. If an application enables hardware
20 * to the stack guard region. As a result, we cannot have a single
21 * background region that enables supervisor read/write access from the
27 /* Region 1 */
32 /* Region 2 */
38 /* Region 3 */
44 /* Region 4 */
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dnxp_mpu_regions.c10 /* Region 0 */
17 * MPU, which means that if one region grants access then another
18 * region cannot revoke access. If an application enables hardware
20 * to the stack guard region. As a result, we cannot have a single
21 * background region that enables supervisor read/write access from the
27 /* Region 1 */
32 /* Region 2 */
38 /* Region 3 */
44 /* Region 4 */
/Zephyr-latest/dts/bindings/base/
Dzephyr,memory-common.yaml7 zephyr,memory-region:
11 memory region in the final executable. The region address and size
15 zephyr,memory-region-flags:
19 memory region. The string set here will be specified in parentheses
22 zephyr,memory-region-mpu:
26 Signify that this node should result in a dedicated MPU region.
32 Attribute or set of attributes (bitmask) for the memory region. See
/Zephyr-latest/soc/nxp/kinetis/k2x/
Dnxp_mpu_regions.c10 /* Region 0 */
20 * MPU, which means that if one region grants access then another
21 * region cannot revoke access. If an application enables hardware
23 * to the stack guard region. As a result, we cannot have a single
24 * background region that enables supervisor read/write access from the
30 /* Region 1 */
35 /* Region 2 */
41 /* Region 3 */
47 /* Region 4 */
/Zephyr-latest/soc/nxp/kinetis/k6x/
Dnxp_mpu_regions.c10 /* Region 0 */
20 * MPU, which means that if one region grants access then another
21 * region cannot revoke access. If an application enables hardware
23 * to the stack guard region. As a result, we cannot have a single
24 * background region that enables supervisor read/write access from the
30 /* Region 1 */
35 /* Region 2 */
41 /* Region 3 */
47 /* Region 4 */
/Zephyr-latest/tests/lib/shared_multi_heap/boards/
Dmps2_an521_cpu0.overlay14 compatible = "zephyr,memory-region", "mmio-sram";
16 zephyr,memory-region = "SSRAM2_3";
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES0";
27 compatible = "zephyr,memory-region", "mmio-sram";
29 zephyr,memory-region = "RES1";
34 compatible = "zephyr,memory-region", "mmio-sram";
36 zephyr,memory-region = "RES2";
Dqemu_cortex_a53.overlay13 compatible = "zephyr,memory-region", "mmio-sram";
15 zephyr,memory-region = "RES0";
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES1";
27 compatible = "zephyr,memory-region", "mmio-sram";
29 zephyr,memory-region = "RES_NO_MPU";
33 compatible = "zephyr,memory-region", "mmio-sram";
35 zephyr,memory-region = "RES2";
/Zephyr-latest/subsys/mem_mgmt/
Dmem_attr.c22 size_t mem_attr_get_regions(const struct mem_attr_region_t **region) in mem_attr_get_regions() argument
24 *region = mem_attr_region; in mem_attr_get_regions()
47 const struct mem_attr_region_t *region = &mem_attr_region[idx]; in mem_attr_check_buf() local
48 size_t region_end = region->dt_addr + region->dt_size; in mem_attr_check_buf()
50 /* Check if the buffer is in the region */ in mem_attr_check_buf()
51 if ((addr >= region->dt_addr) && (addr < region_end)) { in mem_attr_check_buf()
52 /* Check if the buffer is entirely contained in the region */ in mem_attr_check_buf()
55 return (region->dt_attr & attr) == attr ? 0 : -EINVAL; in mem_attr_check_buf()
/Zephyr-latest/include/zephyr/drivers/
Dcoredump.h30 * @brief Structure describing a region in memory that may be
41 /** Address of start of memory region */
44 /** Size of memory region */
71 * region
74 struct coredump_mem_region_node *region);
78 * region
81 struct coredump_mem_region_node *region);
105 * @brief Register a region of memory to be stored in core dump at the
109 * @param region Struct describing memory to be collected
115 struct coredump_mem_region_node *region) in coredump_device_register_memory() argument
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/Zephyr-latest/dts/bindings/reserved-memory/
Dmemory-region.yaml4 # Memory region nodes may be referenced by other device nodes
5 # by adding a memory-region property to the device node.
10 description: List of memory region phandles
12 memory-region-names:
14 description: A list of names, one for each corresponding phandle in memory-region
/Zephyr-latest/arch/arm/core/mpu/
Dnxp_mpu.c28 "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
31 * Global status variable holding the number of HW MPU region indices, which
57 * MPU region start address and size.
64 /* Partition size must be a multiple of the minimum MPU region in mpu_partition_is_valid()
66 * minimum MPU region size. in mpu_partition_is_valid()
81 /* This internal function performs MPU region initialization.
84 * The caller must provide a valid region index.
102 "Region %d base address got 0x%08x expected 0x%08x", in region_init()
106 "Region %d end address got 0x%08x expected 0x%08x", in region_init()
132 /* Attempt to allocate new region index. */ in region_allocate_and_init()
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/Zephyr-latest/include/zephyr/arch/xtensa/
Dxtensa_mmu.h19 * @name Memory region permission and caching mode.
23 /** Memory region is executable. */
26 /** Memory region is writable. */
29 /** Memory region is both executable and writable */
32 /** Memory region has write-back cache. */
35 /** Memory region has write-through cache. */
74 * @brief Software only bit to indicate a memory region can be accessed by user thread(s).
81 * @brief Software only bit to indicate a memory region is shared by all threads.
83 * This BIT tells the mapping code whether the memory region should
93 * Struct used to map a memory region.
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/Zephyr-latest/include/zephyr/kernel/
Dmm.h53 * @name Region permission attributes.
60 /** Region will have read/write access (and not read-only) */
63 /** Region will be executable (normally forbidden) */
66 /** Region will be accessible to user mode (normally supervisor-only) */
72 * @name Region mapping behaviour attributes
77 /** Region will be mapped to 1:1 virtual and physical address */
98 * @brief The mapped region is not guaranteed to be zeroed.
109 * Region will be pinned in memory and never paged
118 * Region will be unpaged i.e. not mapped into memory
160 * K_MEM_PERM_USER flags here; instead manage the region's permissions
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/Zephyr-latest/dts/arm/st/h5/
Dstm32h533Xe.dtsi11 compatible = "zephyr,memory-region", "mmio-sram";
13 zephyr,memory-region = "SRAM1";
17 compatible = "zephyr,memory-region", "mmio-sram";
19 zephyr,memory-region = "SRAM2";
23 compatible = "zephyr,memory-region", "mmio-sram";
25 zephyr,memory-region = "SRAM3";

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