1 /* 2 * Copyright (c) 2017 Linaro Limited. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #include <soc.h> 7 #include <zephyr/arch/arm/mpu/nxp_mpu.h> 8 9 static const struct nxp_mpu_region mpu_regions[] = { 10 /* Region 0 */ 11 /* Debugger access can't be disabled; ENET and USB devices will not be able 12 * to access RAM when their regions are dynamically disabled in NXP MPU. 13 */ 14 MPU_REGION_ENTRY("DEBUGGER_0", 15 0, 16 0xFFFFFFFF, 17 REGION_DEBUGGER_AND_DEVICE_ATTR), 18 19 /* The NXP MPU does not give precedence to memory regions like the ARM 20 * MPU, which means that if one region grants access then another 21 * region cannot revoke access. If an application enables hardware 22 * stack protection, we need to disable supervisor writes from the core 23 * to the stack guard region. As a result, we cannot have a single 24 * background region that enables supervisor read/write access from the 25 * core to the entire address space, and instead define two background 26 * regions that together cover the entire address space except for 27 * SRAM. 28 */ 29 30 /* Region 1 */ 31 MPU_REGION_ENTRY("BACKGROUND_0", 32 0, 33 CONFIG_SRAM_BASE_ADDRESS-1, 34 REGION_BACKGROUND_ATTR), 35 /* Region 2 */ 36 MPU_REGION_ENTRY("BACKGROUND_1", 37 CONFIG_SRAM_BASE_ADDRESS + 38 (CONFIG_SRAM_SIZE * 1024), 39 0xFFFFFFFF, 40 REGION_BACKGROUND_ATTR), 41 /* Region 3 */ 42 MPU_REGION_ENTRY("FLASH_0", 43 CONFIG_FLASH_BASE_ADDRESS, 44 (CONFIG_FLASH_BASE_ADDRESS + 45 (CONFIG_FLASH_SIZE * 1024) - 1), 46 REGION_FLASH_ATTR), 47 /* Region 4 */ 48 MPU_REGION_ENTRY("RAM_U_0", 49 CONFIG_SRAM_BASE_ADDRESS, 50 (CONFIG_SRAM_BASE_ADDRESS + 51 (CONFIG_SRAM_SIZE * 1024) - 1), 52 REGION_RAM_ATTR), 53 }; 54 55 const struct nxp_mpu_config mpu_config = { 56 .num_regions = ARRAY_SIZE(mpu_regions), 57 .mpu_regions = mpu_regions, 58 .sram_region = 4, 59 }; 60
