1 /* 2 * Copyright (c) 2017 Linaro Limited. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #include <soc.h> 7 #include <zephyr/arch/arm/mpu/nxp_mpu.h> 8 9 static const struct nxp_mpu_region mpu_regions[] = { 10 /* Region 0 */ 11 MPU_REGION_ENTRY("DEBUGGER_0", 12 0, 13 0xFFFFFFFF, 14 REGION_DEBUG_ATTR), 15 16 /* The NXP MPU does not give precedence to memory regions like the ARM 17 * MPU, which means that if one region grants access then another 18 * region cannot revoke access. If an application enables hardware 19 * stack protection, we need to disable supervisor writes from the core 20 * to the stack guard region. As a result, we cannot have a single 21 * background region that enables supervisor read/write access from the 22 * core to the entire address space, and instead define two background 23 * regions that together cover the entire address space except for 24 * SRAM. 25 */ 26 27 /* Region 1 */ 28 MPU_REGION_ENTRY("BACKGROUND_0", 29 0, 30 CONFIG_SRAM_BASE_ADDRESS-1, 31 REGION_BACKGROUND_ATTR), 32 /* Region 2 */ 33 MPU_REGION_ENTRY("BACKGROUND_1", 34 CONFIG_SRAM_BASE_ADDRESS + 35 (CONFIG_SRAM_SIZE * 1024), 36 0xFFFFFFFF, 37 REGION_BACKGROUND_ATTR), 38 /* Region 3 */ 39 MPU_REGION_ENTRY("FLASH_0", 40 CONFIG_FLASH_BASE_ADDRESS, 41 (CONFIG_FLASH_BASE_ADDRESS + 42 (CONFIG_FLASH_SIZE * 1024) - 1), 43 REGION_FLASH_ATTR), 44 /* Region 4 */ 45 MPU_REGION_ENTRY("RAM_U_0", 46 CONFIG_SRAM_BASE_ADDRESS, 47 (CONFIG_SRAM_BASE_ADDRESS + 48 (CONFIG_SRAM_SIZE * 1024) - 1), 49 REGION_RAM_ATTR), 50 }; 51 52 const struct nxp_mpu_config mpu_config = { 53 .num_regions = ARRAY_SIZE(mpu_regions), 54 .mpu_regions = mpu_regions, 55 .sram_region = 4, 56 }; 57
