| /Zephyr-latest/drivers/ethernet/ |
| D | eth_sam0_gmac.h | 14 #define GMAC_NCR NCR.reg
15 #define GMAC_NCFGR NCFGR.reg
16 #define GMAC_NSR NSR.reg
17 #define GMAC_UR UR.reg
18 #define GMAC_DCFGR DCFGR.reg
19 #define GMAC_TSR TSR.reg
20 #define GMAC_RBQB RBQB.reg
21 #define GMAC_TBQB TBQB.reg
22 #define GMAC_RSR RSR.reg
23 #define GMAC_ISR ISR.reg
[all …]
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| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | sercom_fixup_samd5x.h | 8 #define MCLK_SERCOM0 (&MCLK->APBAMASK.reg)
12 #define MCLK_SERCOM0 (&MCLK->APBBMASK.reg)
16 #define MCLK_SERCOM0 (&MCLK->APBCMASK.reg)
20 #define MCLK_SERCOM0 (&MCLK->APBDMASK.reg)
25 #define MCLK_SERCOM1 (&MCLK->APBAMASK.reg)
29 #define MCLK_SERCOM1 (&MCLK->APBBMASK.reg)
33 #define MCLK_SERCOM1 (&MCLK->APBCMASK.reg)
37 #define MCLK_SERCOM1 (&MCLK->APBDMASK.reg)
42 #define MCLK_SERCOM2 (&MCLK->APBAMASK.reg)
46 #define MCLK_SERCOM2 (&MCLK->APBBMASK.reg)
[all …]
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| /Zephyr-latest/dts/arm/microchip/mec172x/ |
| D | mec172x-vw-routing.dtsi | 17 vw-reg = <0x02 MSVW 0 0>;
22 vw-reg = <0x02 MSVW 0 1>;
27 vw-reg = <0x02 MSVW 0 2>;
32 vw-reg = <0x03 MSVW 1 0>;
37 vw-reg = <0x03 MSVW 1 1>;
42 vw-reg = <0x03 MSVW 1 2>;
47 vw-reg = <0x07 MSVW 2 0>;
52 vw-reg = <0x07 MSVW 2 1>;
57 vw-reg = <0x07 MSVW 2 2>;
62 vw-reg = <0x41 MSVW 3 0>;
[all …]
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_emsdp.c | 110 uint32_t reg; in pinctrl_emsdp_set() local
117 reg = sys_read32(mux_regs + PMOD_MUX_CTRL); in pinctrl_emsdp_set()
119 reg = sys_read32(mux_regs + ARDUINO_MUX_CTRL); in pinctrl_emsdp_set()
124 reg &= ~(MUX_SEL0_MASK); in pinctrl_emsdp_set()
127 reg |= PM_A_CFG0_GPIO; in pinctrl_emsdp_set()
130 reg |= PM_A_CFG0_UART1a; in pinctrl_emsdp_set()
133 reg |= PM_A_CFG0_UART1b; in pinctrl_emsdp_set()
136 reg |= PM_A_CFG0_SPI; in pinctrl_emsdp_set()
139 reg |= PM_A_CFG0_I2C; in pinctrl_emsdp_set()
142 reg |= PM_A_CFG0_PWM1; in pinctrl_emsdp_set()
[all …]
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| D | pinctrl_nrf.c | 44 #define NRF_PSEL_UART(reg, line) ((NRF_UART_Type *)reg)->PSEL##line argument
47 #define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line argument
51 #define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line argument
54 #define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line argument
60 #define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line argument
62 #define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL.line argument
68 #define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL##line argument
70 #define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL.line argument
74 #define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line argument
78 #define NRF_PSEL_I2S(reg, line) ((NRF_I2S_Type *)reg)->PSEL.line argument
[all …]
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| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | loapic.h | 18 #define LOAPIC_ID 0x020 /* Local APIC ID Reg */
19 #define LOAPIC_VER 0x030 /* Local APIC Version Reg */
20 #define LOAPIC_TPR 0x080 /* Task Priority Reg */
21 #define LOAPIC_APR 0x090 /* Arbitration Priority Reg */
22 #define LOAPIC_PPR 0x0a0 /* Processor Priority Reg */
23 #define LOAPIC_EOI 0x0b0 /* EOI Reg */
24 #define LOAPIC_LDR 0x0d0 /* Logical Destination Reg */
25 #define LOAPIC_DFR 0x0e0 /* Destination Format Reg */
26 #define LOAPIC_SVR 0x0f0 /* Spurious Interrupt Reg */
27 #define LOAPIC_ISR 0x100 /* In-service Reg */
[all …]
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| /Zephyr-latest/drivers/display/ |
| D | display_ili9806e_dsi.c | 32 uint8_t reg; member
39 {.reg = 0xff, .cmd_len = 5, .cmd = {0xFF, 0x98, 0x06, 0x04, 0x01}},
41 {.reg = 0x08, .cmd_len = 1, .cmd = {0x10}},
43 {.reg = 0x21, .cmd_len = 1, .cmd = {0x01}},
45 {.reg = 0x30, .cmd_len = 1, .cmd = {0x01}},
47 {.reg = 0x31, .cmd_len = 1, .cmd = {0x00}},
49 {.reg = 0x40, .cmd_len = 1, .cmd = {0x14}},
51 {.reg = 0x41, .cmd_len = 1, .cmd = {0x33}},
53 {.reg = 0x42, .cmd_len = 1, .cmd = {0x02}},
55 {.reg = 0x43, .cmd_len = 1, .cmd = {0x09}},
[all …]
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| /Zephyr-latest/drivers/dma/ |
| D | dma_gd32.c | 62 uint32_t reg; member
95 gd32_dma_periph_increase_enable(uint32_t reg, dma_channel_enum ch) in gd32_dma_periph_increase_enable() argument
97 GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_PNAGA; in gd32_dma_periph_increase_enable()
101 gd32_dma_periph_increase_disable(uint32_t reg, dma_channel_enum ch) in gd32_dma_periph_increase_disable() argument
103 GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_PNAGA; in gd32_dma_periph_increase_disable()
107 gd32_dma_transfer_set_memory_to_memory(uint32_t reg, dma_channel_enum ch) in gd32_dma_transfer_set_memory_to_memory() argument
109 GD32_DMA_CHCTL(reg, ch) |= GD32_DMA_CHXCTL_M2M; in gd32_dma_transfer_set_memory_to_memory()
110 GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_DIR; in gd32_dma_transfer_set_memory_to_memory()
114 gd32_dma_transfer_set_memory_to_periph(uint32_t reg, dma_channel_enum ch) in gd32_dma_transfer_set_memory_to_periph() argument
116 GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_M2M; in gd32_dma_transfer_set_memory_to_periph()
[all …]
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| /Zephyr-latest/arch/arm64/core/ |
| D | reset.c | 70 uint64_t reg; in z_arm64_el3_init() local
76 reg = 0U; /* Mostly RES0 */ in z_arm64_el3_init()
77 reg &= ~(CPTR_TTA_BIT | /* Do not trap sysreg accesses */ in z_arm64_el3_init()
80 write_cptr_el3(reg); in z_arm64_el3_init()
82 reg = 0U; /* Reset */ in z_arm64_el3_init()
84 reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */ in z_arm64_el3_init()
87 reg |= SCR_EEL2_BIT; /* Enable EL2 secure */ in z_arm64_el3_init()
90 reg |= (SCR_RES1 | /* RES1 */ in z_arm64_el3_init()
95 write_scr_el3(reg); in z_arm64_el3_init()
98 reg = read_sysreg(ICC_SRE_EL3); in z_arm64_el3_init()
[all …]
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| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_xtensa.h | 31 __asm__ volatile("wfr f0, %0\n" :: "r"(regs->fp_non_volatile.reg[0])); in _load_all_float_registers()
32 __asm__ volatile("wfr f1, %0\n" :: "r"(regs->fp_non_volatile.reg[1])); in _load_all_float_registers()
33 __asm__ volatile("wfr f2, %0\n" :: "r"(regs->fp_non_volatile.reg[2])); in _load_all_float_registers()
34 __asm__ volatile("wfr f3, %0\n" :: "r"(regs->fp_non_volatile.reg[3])); in _load_all_float_registers()
35 __asm__ volatile("wfr f4, %0\n" :: "r"(regs->fp_non_volatile.reg[4])); in _load_all_float_registers()
36 __asm__ volatile("wfr f5, %0\n" :: "r"(regs->fp_non_volatile.reg[5])); in _load_all_float_registers()
37 __asm__ volatile("wfr f6, %0\n" :: "r"(regs->fp_non_volatile.reg[6])); in _load_all_float_registers()
38 __asm__ volatile("wfr f7, %0\n" :: "r"(regs->fp_non_volatile.reg[7])); in _load_all_float_registers()
39 __asm__ volatile("wfr f8, %0\n" :: "r"(regs->fp_non_volatile.reg[8])); in _load_all_float_registers()
40 __asm__ volatile("wfr f9, %0\n" :: "r"(regs->fp_non_volatile.reg[9])); in _load_all_float_registers()
[all …]
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| /Zephyr-latest/drivers/counter/ |
| D | counter_andes_atcpit100.c | 16 #define REG_IDR 0x00 /* ID and Revision Reg. */
17 #define REG_CFG 0x10 /* Configuration Reg. */
18 #define REG_INTE 0x14 /* Interrupt Enable Reg. */
19 #define REG_ISTA 0x18 /* Interrupt Status Reg. */
20 #define REG_CHEN 0x1C /* Channel Enable Reg. */
21 #define REG_CTRL0 0x20 /* Channel 0 Control Reg. */
22 #define REG_RELD0 0x24 /* Channel 0 Reload Reg. */
23 #define REG_CNTR0 0x28 /* Channel 0 Counter Reg. */
24 #define REG_CTRL1 0x30 /* Channel 1 Control Reg. */
25 #define REG_RELD1 0x34 /* Channel 1 Reload Reg. */
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/include/adsp/ |
| D | io.h | 15 static inline uint32_t io_reg_read(uint32_t reg) in io_reg_read() argument
17 return sys_read32(reg); in io_reg_read()
20 static inline void io_reg_write(uint32_t reg, uint32_t val) in io_reg_write() argument
22 sys_write32(val, reg); in io_reg_write()
25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
31 static inline uint16_t io_reg_read16(uint32_t reg) in io_reg_read16() argument
33 return sys_read16(reg); in io_reg_read16()
36 static inline void io_reg_write16(uint32_t reg, uint16_t val) in io_reg_write16() argument
38 sys_write16(val, reg); in io_reg_write16()
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| /Zephyr-latest/soc/nxp/imx/imx8x/adsp/include/adsp/ |
| D | io.h | 15 static inline uint32_t io_reg_read(uint32_t reg) in io_reg_read() argument
17 return sys_read32(reg); in io_reg_read()
20 static inline void io_reg_write(uint32_t reg, uint32_t val) in io_reg_write() argument
22 sys_write32(val, reg); in io_reg_write()
25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
31 static inline uint16_t io_reg_read16(uint32_t reg) in io_reg_read16() argument
33 return sys_read16(reg); in io_reg_read16()
36 static inline void io_reg_write16(uint32_t reg, uint16_t val) in io_reg_write16() argument
38 sys_write16(val, reg); in io_reg_write16()
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| /Zephyr-latest/soc/nxp/imx/imx8/adsp/include/adsp/ |
| D | io.h | 15 static inline uint32_t io_reg_read(uint32_t reg) in io_reg_read() argument
17 return sys_read32(reg); in io_reg_read()
20 static inline void io_reg_write(uint32_t reg, uint32_t val) in io_reg_write() argument
22 sys_write32(val, reg); in io_reg_write()
25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
31 static inline uint16_t io_reg_read16(uint32_t reg) in io_reg_read16() argument
33 return sys_read16(reg); in io_reg_read16()
36 static inline void io_reg_write16(uint32_t reg, uint16_t val) in io_reg_write16() argument
38 sys_write16(val, reg); in io_reg_write16()
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| /Zephyr-latest/soc/nxp/imx/imx8m/adsp/include/adsp/ |
| D | io.h | 15 static inline uint32_t io_reg_read(uint32_t reg) in io_reg_read() argument
17 return sys_read32(reg); in io_reg_read()
20 static inline void io_reg_write(uint32_t reg, uint32_t val) in io_reg_write() argument
22 sys_write32(val, reg); in io_reg_write()
25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
31 static inline uint16_t io_reg_read16(uint32_t reg) in io_reg_read16() argument
33 return sys_read16(reg); in io_reg_read16()
36 static inline void io_reg_write16(uint32_t reg, uint16_t val) in io_reg_write16() argument
38 sys_write16(val, reg); in io_reg_write16()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/ |
| D | io.h | 15 static inline uint32_t io_reg_read(uint32_t reg) in io_reg_read() argument
17 return sys_read32(reg); in io_reg_read()
20 static inline void io_reg_write(uint32_t reg, uint32_t val) in io_reg_write() argument
22 sys_write32(val, reg); in io_reg_write()
25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
31 static inline uint16_t io_reg_read16(uint32_t reg) in io_reg_read16() argument
33 return sys_read16(reg); in io_reg_read16()
36 static inline void io_reg_write16(uint32_t reg, uint16_t val) in io_reg_write16() argument
38 sys_write16(val, reg); in io_reg_write16()
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| /Zephyr-latest/dts/arm/microchip/ |
| D | mec5.dtsi | 21 reg = <0>;
27 reg = <0x4000fc00 0x200>;
31 reg = <0x40080100 0x100 0x4000a400 0x100>;
32 reg-names = "pcrr", "vbatr";
37 reg = <0x4000e000 0x400>;
45 reg = <0x0 0x14>;
50 reg = <0x14 0x14>;
55 reg = <0x28 0x14>;
60 reg = <0x3c 0x14>;
65 reg = <0x50 0x14>;
[all …]
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| /Zephyr-latest/tests/drivers/build_all/sensor/ |
| D | i2c.dtsi | 30 * PLEASE KEEP REG ADDRESSES SEQUENTIAL *
35 reg = <0x0>;
41 reg = <0x1>;
46 reg = <0x2>;
52 reg = <0x3>;
60 reg = <0x4>;
65 reg = <0x5>;
70 reg = <0x6>;
75 reg = <0x7>;
81 reg = <0x8>;
[all …]
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| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv32-fe310.dtsi | 32 reg = <0>;
53 reg = <0x10000000 0x40>;
54 reg-names = "control";
60 reg = <0x10000040 0x9c0>;
61 reg-names = "control";
66 reg = <0x2000000 0x10000>;
71 reg = <0x0 0x1000>;
72 reg-names = "control";
76 reg = <0x80000000 0x4000>;
77 reg-names = "mem";
[all …]
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_andes_atciic100.c | 45 uint32_t reg = 0; in i2c_atciic100_default_control() local
51 reg = sys_read32(I2C_CMD(dev)); in i2c_atciic100_default_control()
52 reg &= (~CMD_MSK); in i2c_atciic100_default_control()
53 reg |= (CMD_RESET_I2C); in i2c_atciic100_default_control()
54 sys_write32(reg, I2C_CMD(dev)); in i2c_atciic100_default_control()
57 reg = sys_read32(I2C_CFG(dev)); in i2c_atciic100_default_control()
58 switch (reg & 0x3) { in i2c_atciic100_default_control()
78 reg = sys_read32(I2C_SET(dev)); in i2c_atciic100_default_control()
79 reg |= ((SETUP_T_SUDAT_STD << 24) | in i2c_atciic100_default_control()
86 sys_write32(reg, I2C_SET(dev)); in i2c_atciic100_default_control()
[all …]
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| /Zephyr-latest/tests/drivers/build_all/led/ |
| D | app.overlay | 21 reg = <0xdeadbeef 0x1000>;
37 reg = <0x11112222 0x1000>;
43 reg = <0x1>;
50 reg = <0x2>;
55 reg = <0x3>;
60 reg = <0x4>;
65 reg = <0x5>;
70 reg = <0x6>;
75 reg = <0x7>;
80 reg = <0x8>;
[all …]
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| /Zephyr-latest/soc/brcm/bcmvk/viper/a72/ |
| D | plat_core.c | 14 uint64_t reg, val; in z_arm64_el3_plat_init() local
17 reg = read_actlr_el3(); in z_arm64_el3_plat_init()
18 reg |= (ACTLR_EL3_L2ACTLR_BIT | in z_arm64_el3_plat_init()
23 write_actlr_el3(reg); in z_arm64_el3_plat_init()
25 reg = read_sysreg(CORTEX_A72_L2ACTLR_EL1); in z_arm64_el3_plat_init()
26 reg |= CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT; in z_arm64_el3_plat_init()
27 write_sysreg(reg, CORTEX_A72_L2ACTLR_EL1); in z_arm64_el3_plat_init()
38 reg &= ~val; in z_arm64_el3_plat_init()
47 reg |= val; in z_arm64_el3_plat_init()
49 write_sysreg(reg, CORTEX_A72_L2CTLR_EL1); in z_arm64_el3_plat_init()
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| /Zephyr-latest/boards/nordic/nrf54h20dk/ |
| D | nrf54h20dk_nrf54h20-memory_map.dtsi | 12 reg = <0x2f010000 DT_SIZE_K(4)>;
20 reg = <0x0 DT_SIZE_K(2)>;
24 reg = <0x800 DT_SIZE_K(2)>;
30 reg = <0x2f011000 DT_SIZE_K(260)>;
38 reg = <0x0 DT_SIZE_K(2)>;
42 reg = <0x800 DT_SIZE_K(2)>;
46 reg = <0x1000 DT_SIZE_K(256)>;
52 reg = <0x2f0be000 DT_SIZE_K(4)>;
61 reg = <0x0 DT_SIZE_K(4)>;
67 reg = <0x2f0bf000 DT_SIZE_K(4)>;
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat1a/psoc6_01/ |
| D | psoc6_01.dtsi | 18 reg = <0>;
23 reg = <1>;
29 reg = < 0x40250000 0x10000 >;
35 reg = <0x10000000 0x100000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x48000>;
55 reg = <0x40310000 0x20000>;
62 reg = <0x40310000 0x4000>;
69 reg = <0x40320000 0x80>;
78 reg = <0x40320080 0x80>;
[all …]
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| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_cavs25.dtsi | 18 reg = <0>;
27 reg = <1>;
34 reg = <2>;
41 reg = <3>;
63 reg = <0xbe000000 DT_SIZE_K(2944)>;
69 reg = <0xbe800000 DT_SIZE_K(64)>;
104 reg = <0xB0000000 DT_SIZE_M(16)>;
112 reg = <0x71d50 0x10>;
117 reg = <0x71d10 0x10>;
122 reg = <0x71f00 0x100>;
[all …]
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