1/*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
7
8/ {
9	reserved-memory {
10		cpurad_ram0x_region: memory@2f010000 {
11			compatible = "nordic,owned-memory";
12			reg = <0x2f010000 DT_SIZE_K(4)>;
13			status = "disabled";
14			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
15			#address-cells = <1>;
16			#size-cells = <1>;
17			ranges = <0x0 0x2f010000 0x1000>;
18
19			cpusec_cpurad_ipc_shm: memory@0 {
20				reg = <0x0 DT_SIZE_K(2)>;
21			};
22
23			cpurad_cpusec_ipc_shm: memory@800 {
24				reg = <0x800 DT_SIZE_K(2)>;
25			};
26		};
27
28		cpuapp_ram0x_region: memory@2f011000 {
29			compatible = "nordic,owned-memory";
30			reg = <0x2f011000 DT_SIZE_K(260)>;
31			status = "disabled";
32			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
33			#address-cells = <1>;
34			#size-cells = <1>;
35			ranges = <0x0 0x2f011000 0x41000>;
36
37			cpusec_cpuapp_ipc_shm: memory@0 {
38				reg = <0x0 DT_SIZE_K(2)>;
39			};
40
41			cpuapp_cpusec_ipc_shm: memory@800 {
42				reg = <0x800 DT_SIZE_K(2)>;
43			};
44
45			cpuapp_data: memory@1000 {
46				reg = <0x1000 DT_SIZE_K(256)>;
47			};
48		};
49
50		etr_buf_ram0x_region: memory@2f0be000 {
51			compatible = "nordic,owned-memory";
52			reg = <0x2f0be000 DT_SIZE_K(4)>;
53			status = "disabled";
54			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
55			#address-cells = <1>;
56			#size-cells = <1>;
57			ranges = <0x0 0x2f0be000 0x1000>;
58
59			/* TODO In future move this region to cpuapp_ram0x_region. */
60			etr_buffer: memory@0 {
61				reg = <0x0 DT_SIZE_K(4)>;
62			};
63		};
64
65		cpuapp_cpurad_ram0x_region: memory@2f0bf000 {
66			compatible = "nordic,owned-memory";
67			reg = <0x2f0bf000 DT_SIZE_K(4)>;
68			status = "disabled";
69			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>,
70					<NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
71			#address-cells = <1>;
72			#size-cells = <1>;
73			ranges = <0x0 0x2f0bf000 0x1000>;
74
75			cpuapp_cpurad_ipc_shm: memory@0 {
76				reg = <0x0 DT_SIZE_K(2)>;
77			};
78
79			cpurad_cpuapp_ipc_shm: memory@800 {
80				reg = <0x800 DT_SIZE_K(2)>;
81			};
82		};
83
84		cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
85			reg = <0x2f88fce0 0x80>;
86		};
87
88		cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
89			reg = <0x2f88fd60 0x80>;
90		};
91
92		cpurad_cpusys_ipc_shm: memory@2f88fe00 {
93			reg = <0x2f88fe00 0x80>;
94		};
95
96		cpusys_cpurad_ipc_shm: memory@2f88fe80 {
97			reg = <0x2f88fe80 0x80>;
98		};
99
100		/*
101		 * NOTE: FLPR has a direct bridge with RAM21 that bypasses MPC.
102		 * This means that when this region is marked as non-executable,
103		 * only FLPR can execute code from it.
104		 */
105		ram21_region: memory@2f890000 {
106			compatible = "nordic,owned-memory";
107			status = "disabled";
108			reg = <0x2f890000 DT_SIZE_K(64)>;
109			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
110			#address-cells = <1>;
111			#size-cells = <1>;
112			ranges = <0x0 0x2f890000 0x10000>;
113
114			cpuflpr_code_data: memory@0 {
115				reg = <0x0 DT_SIZE_K(46)>;
116			};
117
118			cpuapp_cpuflpr_ipc_shm: memory@b800 {
119				reg = <0xb800 DT_SIZE_K(1)>;
120			};
121
122			cpuflpr_cpuapp_ipc_shm: memory@bc00 {
123				reg = <0xbc00 DT_SIZE_K(1)>;
124			};
125
126			dma_fast_region: memory@c000 {
127				compatible = "zephyr,memory-region";
128				reg = <0xc000 DT_SIZE_K(16)>;
129				status = "disabled";
130				#memory-region-cells = <0>;
131				zephyr,memory-region = "DMA_RAM21";
132				zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>;
133			};
134		};
135
136		cpuppr_ram3x_region: memory@2fc00000 {
137			compatible = "nordic,owned-memory";
138			reg = <0x2fc00000 DT_SIZE_K(64)>;
139			status = "disabled";
140			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWX>;
141			#address-cells = <1>;
142			#size-cells = <1>;
143			ranges = <0x0 0x2fc00000 0x10000>;
144
145			cpuppr_code_data: memory@0 {
146				reg = <0x0 DT_SIZE_K(62)>;
147			};
148
149			cpuapp_cpuppr_ipc_shm: memory@f800 {
150				reg = <0xf800 DT_SIZE_K(1)>;
151			};
152
153			cpuppr_cpuapp_ipc_shm: memory@fc00 {
154				reg = <0xfc00 DT_SIZE_K(1)>;
155			};
156		};
157
158		cpuapp_dma_region: memory@2fc12000 {
159			compatible = "nordic,owned-memory", "zephyr,memory-region";
160			reg = <0x2fc12000 DT_SIZE_K(4)>;
161			status = "disabled";
162			#memory-region-cells = <0>;
163			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>;
164			zephyr,memory-region = "DMA_RAM3x_APP";
165			zephyr,memory-attr = <( DT_MEM_DMA )>;
166		};
167
168		cpurad_dma_region: memory@2fc13000 {
169			compatible = "nordic,owned-memory", "zephyr,memory-region";
170			reg = <0x2fc13000 DT_SIZE_K(1)>;
171			status = "disabled";
172			#memory-region-cells = <0>;
173			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
174			zephyr,memory-region = "DMA_RAM3x_RAD";
175			zephyr,memory-attr = <( DT_MEM_DMA )>;
176		};
177	};
178};
179
180&mram1x {
181	cpurad_rx_partitions: cpurad-rx-partitions {
182		compatible = "nordic,owned-partitions", "fixed-partitions";
183		status = "disabled";
184		nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>;
185		#address-cells = <1>;
186		#size-cells = <1>;
187
188		cpurad_slot0_partition: partition@54000 {
189			reg = <0x54000 DT_SIZE_K(256)>;
190		};
191	};
192
193	cpuapp_rx_partitions: cpuapp-rx-partitions {
194		compatible = "nordic,owned-partitions", "fixed-partitions";
195		status = "disabled";
196		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
197		#address-cells = <1>;
198		#size-cells = <1>;
199
200		cpuapp_slot0_partition: partition@94000 {
201			reg = <0x94000 DT_SIZE_K(320)>;
202		};
203
204		cpuppr_code_partition: partition@e4000 {
205			reg = <0xe4000 DT_SIZE_K(64)>;
206		};
207
208		cpuflpr_code_partition: partition@f4000 {
209			reg = <0xf4000 DT_SIZE_K(48)>;
210		};
211	};
212
213	cpuapp_rw_partitions: cpuapp-rw-partitions {
214		compatible = "nordic,owned-partitions", "fixed-partitions";
215		status = "disabled";
216		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
217		#address-cells = <1>;
218		#size-cells = <1>;
219
220		dfu_partition: partition@100000 {
221			reg = < 0x100000 DT_SIZE_K(908) >;
222		};
223
224		storage_partition: partition@1e3000 {
225			reg = < 0x1e3000 DT_SIZE_K(40) >;
226		};
227	};
228};
229