/*
 * Copyright (c) 2024 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>

/ {
	reserved-memory {
		cpurad_ram0x_region: memory@2f010000 {
			compatible = "nordic,owned-memory";
			reg = <0x2f010000 DT_SIZE_K(4)>;
			status = "disabled";
			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2f010000 0x1000>;

			cpusec_cpurad_ipc_shm: memory@0 {
				reg = <0x0 DT_SIZE_K(2)>;
			};

			cpurad_cpusec_ipc_shm: memory@800 {
				reg = <0x800 DT_SIZE_K(2)>;
			};
		};

		cpuapp_ram0x_region: memory@2f011000 {
			compatible = "nordic,owned-memory";
			reg = <0x2f011000 DT_SIZE_K(260)>;
			status = "disabled";
			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2f011000 0x41000>;

			cpusec_cpuapp_ipc_shm: memory@0 {
				reg = <0x0 DT_SIZE_K(2)>;
			};

			cpuapp_cpusec_ipc_shm: memory@800 {
				reg = <0x800 DT_SIZE_K(2)>;
			};

			cpuapp_data: memory@1000 {
				reg = <0x1000 DT_SIZE_K(256)>;
			};
		};

		etr_buf_ram0x_region: memory@2f0be000 {
			compatible = "nordic,owned-memory";
			reg = <0x2f0be000 DT_SIZE_K(4)>;
			status = "disabled";
			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2f0be000 0x1000>;

			/* TODO In future move this region to cpuapp_ram0x_region. */
			etr_buffer: memory@0 {
				reg = <0x0 DT_SIZE_K(4)>;
			};
		};

		cpuapp_cpurad_ram0x_region: memory@2f0bf000 {
			compatible = "nordic,owned-memory";
			reg = <0x2f0bf000 DT_SIZE_K(4)>;
			status = "disabled";
			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>,
					<NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2f0bf000 0x1000>;

			cpuapp_cpurad_ipc_shm: memory@0 {
				reg = <0x0 DT_SIZE_K(2)>;
			};

			cpurad_cpuapp_ipc_shm: memory@800 {
				reg = <0x800 DT_SIZE_K(2)>;
			};
		};

		cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
			reg = <0x2f88fce0 0x80>;
		};

		cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
			reg = <0x2f88fd60 0x80>;
		};

		cpurad_cpusys_ipc_shm: memory@2f88fe00 {
			reg = <0x2f88fe00 0x80>;
		};

		cpusys_cpurad_ipc_shm: memory@2f88fe80 {
			reg = <0x2f88fe80 0x80>;
		};

		/*
		 * NOTE: FLPR has a direct bridge with RAM21 that bypasses MPC.
		 * This means that when this region is marked as non-executable,
		 * only FLPR can execute code from it.
		 */
		ram21_region: memory@2f890000 {
			compatible = "nordic,owned-memory";
			status = "disabled";
			reg = <0x2f890000 DT_SIZE_K(64)>;
			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2f890000 0x10000>;

			cpuflpr_code_data: memory@0 {
				reg = <0x0 DT_SIZE_K(46)>;
			};

			cpuapp_cpuflpr_ipc_shm: memory@b800 {
				reg = <0xb800 DT_SIZE_K(1)>;
			};

			cpuflpr_cpuapp_ipc_shm: memory@bc00 {
				reg = <0xbc00 DT_SIZE_K(1)>;
			};

			dma_fast_region: memory@c000 {
				compatible = "zephyr,memory-region";
				reg = <0xc000 DT_SIZE_K(16)>;
				status = "disabled";
				#memory-region-cells = <0>;
				zephyr,memory-region = "DMA_RAM21";
				zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>;
			};
		};

		cpuppr_ram3x_region: memory@2fc00000 {
			compatible = "nordic,owned-memory";
			reg = <0x2fc00000 DT_SIZE_K(64)>;
			status = "disabled";
			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWX>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2fc00000 0x10000>;

			cpuppr_code_data: memory@0 {
				reg = <0x0 DT_SIZE_K(62)>;
			};

			cpuapp_cpuppr_ipc_shm: memory@f800 {
				reg = <0xf800 DT_SIZE_K(1)>;
			};

			cpuppr_cpuapp_ipc_shm: memory@fc00 {
				reg = <0xfc00 DT_SIZE_K(1)>;
			};
		};

		cpuapp_dma_region: memory@2fc12000 {
			compatible = "nordic,owned-memory", "zephyr,memory-region";
			reg = <0x2fc12000 DT_SIZE_K(4)>;
			status = "disabled";
			#memory-region-cells = <0>;
			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>;
			zephyr,memory-region = "DMA_RAM3x_APP";
			zephyr,memory-attr = <( DT_MEM_DMA )>;
		};

		cpurad_dma_region: memory@2fc13000 {
			compatible = "nordic,owned-memory", "zephyr,memory-region";
			reg = <0x2fc13000 DT_SIZE_K(1)>;
			status = "disabled";
			#memory-region-cells = <0>;
			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
			zephyr,memory-region = "DMA_RAM3x_RAD";
			zephyr,memory-attr = <( DT_MEM_DMA )>;
		};

		xip_region: memory@60000000 {
			compatible = "nordic,owned-memory";
			reg = <0x60000000 0x20000000>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x60000000 0x20000000>;
		};
	};
};

&mram1x {
	cpurad_rx_partitions: cpurad-rx-partitions {
		compatible = "nordic,owned-partitions", "fixed-partitions";
		status = "disabled";
		nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>;
		#address-cells = <1>;
		#size-cells = <1>;

		cpurad_slot0_partition: partition@54000 {
			reg = <0x54000 DT_SIZE_K(256)>;
		};
	};

	cpuapp_rx_partitions: cpuapp-rx-partitions {
		compatible = "nordic,owned-partitions", "fixed-partitions";
		status = "disabled";
		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
		#address-cells = <1>;
		#size-cells = <1>;

		cpuapp_slot0_partition: partition@94000 {
			reg = <0x94000 DT_SIZE_K(320)>;
		};

		cpuppr_code_partition: partition@e4000 {
			reg = <0xe4000 DT_SIZE_K(64)>;
		};

		cpuflpr_code_partition: partition@f4000 {
			reg = <0xf4000 DT_SIZE_K(48)>;
		};
	};

	cpuapp_rw_partitions: cpuapp-rw-partitions {
		compatible = "nordic,owned-partitions", "fixed-partitions";
		status = "disabled";
		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
		#address-cells = <1>;
		#size-cells = <1>;

		dfu_partition: partition@100000 {
			reg = < 0x100000 DT_SIZE_K(908) >;
		};

		storage_partition: partition@1e3000 {
			reg = < 0x1e3000 DT_SIZE_K(40) >;
		};
	};
};