45 	uint32_t reg = 0;  in i2c_atciic100_default_control()  local
51 	reg = sys_read32(I2C_CMD(dev));  in i2c_atciic100_default_control()
52 	reg &= (~CMD_MSK);  in i2c_atciic100_default_control()
53 	reg |= (CMD_RESET_I2C);  in i2c_atciic100_default_control()
54 	sys_write32(reg, I2C_CMD(dev));  in i2c_atciic100_default_control()
57 	reg = sys_read32(I2C_CFG(dev));  in i2c_atciic100_default_control()
58 	switch (reg & 0x3) {  in i2c_atciic100_default_control()
78 	reg = sys_read32(I2C_SET(dev));  in i2c_atciic100_default_control()
79 	reg |= ((SETUP_T_SUDAT_STD << 24)	|  in i2c_atciic100_default_control()
86 	sys_write32(reg, I2C_SET(dev));  in i2c_atciic100_default_control()
98 	uint32_t reg = 0;  in i2c_atciic100_configure()  local
101 	reg = sys_read32(I2C_SET(dev));  in i2c_atciic100_configure()
105 		reg |= SETUP_SPEED_STD;  in i2c_atciic100_configure()
109 		reg |= SETUP_SPEED_FAST;  in i2c_atciic100_configure()
113 		reg |= SETUP_SPEED_FAST_PLUS;  in i2c_atciic100_configure()
126 		reg |= SETUP_CONTROLLER;  in i2c_atciic100_configure()
129 		reg &= ~SETUP_CONTROLLER;  in i2c_atciic100_configure()
134 		reg |= SETUP_ADDRESSING;  in i2c_atciic100_configure()
136 		reg &= ~SETUP_ADDRESSING;  in i2c_atciic100_configure()
139 	sys_write32(reg, I2C_SET(dev));  in i2c_atciic100_configure()
205 	uint32_t reg = 0;  in i2c_atciic100_controller_send()  local
217 	reg = sys_read32(I2C_INTE(dev));  in i2c_atciic100_controller_send()
218 	reg &= (~IEN_ALL);  in i2c_atciic100_controller_send()
219 	sys_write32(reg, I2C_INTE(dev));  in i2c_atciic100_controller_send()
222 	reg = sys_read32(I2C_SET(dev));  in i2c_atciic100_controller_send()
223 	reg |= SETUP_CONTROLLER;  in i2c_atciic100_controller_send()
224 	sys_write32(reg, I2C_SET(dev));  in i2c_atciic100_controller_send()
232 	reg = sys_read32(I2C_CMD(dev));  in i2c_atciic100_controller_send()
233 	reg &= (~CMD_MSK);  in i2c_atciic100_controller_send()
234 	reg |= (CMD_CLEAR_FIFO);  in i2c_atciic100_controller_send()
235 	sys_write32(reg, I2C_CMD(dev));  in i2c_atciic100_controller_send()
246 	reg = sys_read32(I2C_CTRL(dev));  in i2c_atciic100_controller_send()
247 	reg &= (~(CTRL_PHASE_START | CTRL_PHASE_ADDR | CTRL_PHASE_STOP |  in i2c_atciic100_controller_send()
251 		reg |= CTRL_PHASE_STOP;  in i2c_atciic100_controller_send()
254 		reg |= (CTRL_PHASE_START | CTRL_PHASE_ADDR);  in i2c_atciic100_controller_send()
257 		reg |= (CTRL_PHASE_DATA | (num & CTRL_DATA_COUNT));  in i2c_atciic100_controller_send()
260 	sys_write32(reg, I2C_CTRL(dev));  in i2c_atciic100_controller_send()
269 	reg = sys_read32(I2C_ADDR(dev));  in i2c_atciic100_controller_send()
270 	reg &= (~TARGET_ADDR_MSK);  in i2c_atciic100_controller_send()
271 	reg |= (dev_data->target_addr & (TARGET_ADDR_MSK));  in i2c_atciic100_controller_send()
272 	sys_write32(reg, I2C_ADDR(dev));  in i2c_atciic100_controller_send()
279 	reg = sys_read32(I2C_INTE(dev));  in i2c_atciic100_controller_send()
283 	reg |= (IEN_CMPL | IEN_ARB_LOSE | IEN_ADDR_HIT);  in i2c_atciic100_controller_send()
286 		reg |= IEN_FIFO_EMPTY;  in i2c_atciic100_controller_send()
288 		reg &= (~IEN_FIFO_EMPTY);  in i2c_atciic100_controller_send()
291 	sys_write32(reg, I2C_INTE(dev));  in i2c_atciic100_controller_send()
297 	reg = sys_read32(I2C_CMD(dev));  in i2c_atciic100_controller_send()
298 	reg &= (~CMD_MSK);  in i2c_atciic100_controller_send()
299 	reg |= (CMD_ISSUE_TRANSACTION);  in i2c_atciic100_controller_send()
300 	sys_write32(reg, I2C_CMD(dev));  in i2c_atciic100_controller_send()
315 	uint32_t reg = 0;  in i2c_atciic100_controller_receive()  local
327 	reg = sys_read32(I2C_INTE(dev));  in i2c_atciic100_controller_receive()
328 	reg &= (~IEN_ALL);  in i2c_atciic100_controller_receive()
329 	sys_write32(reg, I2C_INTE(dev));  in i2c_atciic100_controller_receive()
332 	reg = sys_read32(I2C_SET(dev));  in i2c_atciic100_controller_receive()
333 	reg |= SETUP_CONTROLLER;  in i2c_atciic100_controller_receive()
334 	sys_write32(reg, I2C_SET(dev));  in i2c_atciic100_controller_receive()
342 	reg = sys_read32(I2C_CMD(dev));  in i2c_atciic100_controller_receive()
343 	reg &= (~CMD_MSK);  in i2c_atciic100_controller_receive()
344 	reg |= (CMD_CLEAR_FIFO);  in i2c_atciic100_controller_receive()
345 	sys_write32(reg, I2C_CMD(dev));  in i2c_atciic100_controller_receive()
356 	reg = sys_read32(I2C_CTRL(dev));  in i2c_atciic100_controller_receive()
357 	reg &= (~(CTRL_PHASE_START | CTRL_PHASE_ADDR | CTRL_PHASE_STOP |  in i2c_atciic100_controller_receive()
359 	reg |= (CTRL_PHASE_START | CTRL_PHASE_ADDR | CTRL_DIR);  in i2c_atciic100_controller_receive()
362 		reg |= CTRL_PHASE_STOP;  in i2c_atciic100_controller_receive()
365 		reg |= (CTRL_PHASE_DATA | (num & CTRL_DATA_COUNT));  in i2c_atciic100_controller_receive()
368 	sys_write32(reg, I2C_CTRL(dev));  in i2c_atciic100_controller_receive()
377 	reg = sys_read32(I2C_ADDR(dev));  in i2c_atciic100_controller_receive()
378 	reg &= (~TARGET_ADDR_MSK);  in i2c_atciic100_controller_receive()
379 	reg |= (dev_data->target_addr & (TARGET_ADDR_MSK));  in i2c_atciic100_controller_receive()
380 	sys_write32(reg, I2C_ADDR(dev));  in i2c_atciic100_controller_receive()
386 	reg = sys_read32(I2C_INTE(dev));  in i2c_atciic100_controller_receive()
387 	reg |= (IEN_CMPL | IEN_FIFO_FULL | IEN_ARB_LOSE | IEN_ADDR_HIT);  in i2c_atciic100_controller_receive()
388 	sys_write32(reg, I2C_INTE(dev));  in i2c_atciic100_controller_receive()
394 	reg = sys_read32(I2C_CMD(dev));  in i2c_atciic100_controller_receive()
395 	reg &= (~CMD_MSK);  in i2c_atciic100_controller_receive()
396 	reg |= (CMD_ISSUE_TRANSACTION);  in i2c_atciic100_controller_receive()
397 	sys_write32(reg, I2C_CMD(dev));  in i2c_atciic100_controller_receive()
411 	uint32_t reg = 0;  in i2c_atciic100_target_send()  local
414 	reg = sys_read32(I2C_CMD(dev));  in i2c_atciic100_target_send()
415 	reg &= (~CMD_MSK);  in i2c_atciic100_target_send()
416 	reg |= (CMD_CLEAR_FIFO);  in i2c_atciic100_target_send()
417 	sys_write32(reg, I2C_CMD(dev));  in i2c_atciic100_target_send()
433 	uint32_t i = 0, write_fifo_count = 0, reg = 0;  in i2c_controller_fifo_write()  local
456 			reg = sys_read32(I2C_INTE(dev));  in i2c_controller_fifo_write()
457 			reg &= (~IEN_FIFO_EMPTY);  in i2c_controller_fifo_write()
458 			sys_write32(reg, I2C_INTE(dev));  in i2c_controller_fifo_write()
467 	uint32_t i = 0, read_fifo_count = 0, reg = 0;  in i2c_controller_fifo_read()  local
487 			reg = sys_read32(I2C_INTE(dev));  in i2c_controller_fifo_read()
488 			reg &= (~IEN_FIFO_FULL);  in i2c_controller_fifo_read()
489 			sys_write32(reg, I2C_INTE(dev));  in i2c_controller_fifo_read()
515 	uint32_t reg_set = 0, reg_ctrl = 0, reg = 0;  in i2c_cmpl_handler()  local
522 		reg = sys_read32(I2C_INTE(dev));  in i2c_cmpl_handler()
523 		reg &= (~IEN_ALL);  in i2c_cmpl_handler()
524 		sys_write32(reg, I2C_INTE(dev));  in i2c_cmpl_handler()
573 	reg = 0x0;  in i2c_cmpl_handler()
574 	reg |= (IEN_CMPL | IEN_ADDR_HIT | STATUS_BYTE_RECV | STATUS_BYTE_TRANS);  in i2c_cmpl_handler()
575 	sys_write32(reg, I2C_INTE(dev));  in i2c_cmpl_handler()
577 	reg = sys_read32(I2C_SET(dev));  in i2c_cmpl_handler()
578 	reg &= ~(SETUP_CONTROLLER);  in i2c_cmpl_handler()
579 	sys_write32(reg, I2C_SET(dev));  in i2c_cmpl_handler()
581 	reg &= (~TARGET_ADDR_MSK);  in i2c_cmpl_handler()
582 	reg |= (dev_data->target_config->address & (TARGET_ADDR_MSK));  in i2c_cmpl_handler()
583 	sys_write32(reg, I2C_ADDR(dev));  in i2c_cmpl_handler()
657 	uint32_t reg;  in i2c_atciic100_target_register()  local
669 	reg = 0x0;  in i2c_atciic100_target_register()
670 	reg |= (IEN_CMPL | IEN_ADDR_HIT | STATUS_BYTE_RECV | STATUS_BYTE_TRANS);  in i2c_atciic100_target_register()
671 	sys_write32(reg, I2C_INTE(dev));  in i2c_atciic100_target_register()
679 	uint32_t reg;  in i2c_atciic100_target_unregister()  local
682 	reg = sys_read32(I2C_INTE(dev));  in i2c_atciic100_target_unregister()
683 	reg &= (~IEN_ALL);  in i2c_atciic100_target_unregister()
684 	sys_write32(reg, I2C_INTE(dev));  in i2c_atciic100_target_unregister()