70 	uint64_t reg;  in z_arm64_el3_init()  local
76 	reg = 0U;			/* Mostly RES0 */  in z_arm64_el3_init()
77 	reg &= ~(CPTR_TTA_BIT |		/* Do not trap sysreg accesses */  in z_arm64_el3_init()
80 	write_cptr_el3(reg);  in z_arm64_el3_init()
82 	reg = 0U;			/* Reset */  in z_arm64_el3_init()
84 	reg |= SCR_NS_BIT;		/* EL2 / EL3 non-secure */  in z_arm64_el3_init()
87 		reg |= SCR_EEL2_BIT;    /* Enable EL2 secure */  in z_arm64_el3_init()
90 	reg |= (SCR_RES1 |		/* RES1 */  in z_arm64_el3_init()
95 	write_scr_el3(reg);  in z_arm64_el3_init()
98 	reg = read_sysreg(ICC_SRE_EL3);  in z_arm64_el3_init()
99 	reg |= (ICC_SRE_ELx_DFB_BIT |	/* Disable FIQ bypass */  in z_arm64_el3_init()
103 	write_sysreg(reg, ICC_SRE_EL3);  in z_arm64_el3_init()
122 	uint64_t reg;  in z_arm64_el2_init()  local
124 	reg = read_sctlr_el2();  in z_arm64_el2_init()
125 	reg |= (SCTLR_EL2_RES1 |	/* RES1 */  in z_arm64_el2_init()
128 	write_sctlr_el2(reg);  in z_arm64_el2_init()
130 	reg = read_hcr_el2();  in z_arm64_el2_init()
136 	reg &= ~(HCR_IMO_BIT | HCR_AMO_BIT | HCR_TGE_BIT);  in z_arm64_el2_init()
137 	reg |= HCR_RW_BIT;		/* EL1 Execution state is AArch64 */  in z_arm64_el2_init()
138 	write_hcr_el2(reg);  in z_arm64_el2_init()
140 	reg = 0U;			/* RES0 */  in z_arm64_el2_init()
141 	reg |= CPTR_EL2_RES1;		/* RES1 */  in z_arm64_el2_init()
142 	reg &= ~(CPTR_TFP_BIT |		/* Do not trap SVE, SIMD and FP */  in z_arm64_el2_init()
144 	write_cptr_el2(reg);  in z_arm64_el2_init()
155 	reg = read_mpidr_el1();  in z_arm64_el2_init()
156 	write_vmpidr_el2(reg);  in z_arm64_el2_init()
171 	uint64_t reg;  in z_arm64_el1_init()  local
177 	reg = 0U;			/* RES0 */  in z_arm64_el1_init()
178 	reg |= CPACR_EL1_FPEN_NOTRAP;	/* Do not trap NEON/SIMD/FP initially */  in z_arm64_el1_init()
180 	write_cpacr_el1(reg);  in z_arm64_el1_init()
182 	reg = read_sctlr_el1();  in z_arm64_el1_init()
183 	reg |= (SCTLR_EL1_RES1 |	/* RES1 */  in z_arm64_el1_init()
187 	write_sctlr_el1(reg);  in z_arm64_el1_init()