Searched +full:pinctrl +full:- +full:n (Results 1 – 25 of 430) sorted by relevance
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| /Zephyr-latest/include/zephyr/devicetree/ |
| D | pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
15 * @defgroup devicetree-pinctrl Pin control
21 * @brief Get a node identifier for a phandle in a pinctrl property by index
25 * n: node {
26 * pinctrl-0 = <&foo &bar>;
27 * pinctrl-1 = <&baz &blub>;
32 * DT_PINCTRL_BY_IDX(DT_NODELABEL(n), 0, 1) // DT_NODELABEL(bar)
33 * DT_PINCTRL_BY_IDX(DT_NODELABEL(n), 1, 0) // DT_NODELABEL(baz)
35 * @param node_id node with a pinctrl-'pc_idx' property
36 * @param pc_idx index of the pinctrl property itself
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,stm32-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-qdec"
9 - name: base.yaml
10 - name: pinctrl-device.yaml
13 pinctrl-0:
16 pinctrl-names:
19 st,encoder-mode:
37 - 0x1
38 - 0x2
39 - 0x3
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| /Zephyr-latest/scripts/utils/ |
| D | pinctrl_nrf_migrate.py | 4 # SPDX-License-Identifier: Apache-2.0
7 Pinctrl Migration Utility Script for nRF Boards
11 nRF-based boards using the old <signal>-pin properties to select peripheral
13 file by removing old pin-related properties replacing them with pinctrl states.
14 A board-pinctrl.dtsi file will be generated containing the configuration for
15 all pinctrl states. Note that script will also work on files that have been
28 -i path/to/board.dts
29 [--no-backup]
30 [--skip-nrf-check]
31 [--header ""]
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| /Zephyr-latest/soc/infineon/cat1a/psoc6_legacy/ |
| D | cypress_psoc6_dt.h | 3 * Copyright (c) 2020-2021 ATL Electronics
5 * SPDX-License-Identifier: Apache-2.0
23 * because Cortex-M0+ can handle a limited number of interrupts and have
34 * #define <DRIVER>_PSOC6_INIT(n) \
38 * CY_PSOC6_DT_INST_NVIC_INSTALL(n, \
44 * n - driver instance number
45 * isr - isr function to be called
47 * Cortex-M4 simple pass the parameter and constructs an usual NVIC
50 * The Cortex-M0+ must get from interrupt parent the interrupt line and
52 * Cortex-M0+ NVIC. The multiplexer is configured by CY_PSOC6_DT_NVIC_MUX_MAP
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nuvoton,numaker-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 The node has the 'pinctrl' node label set in your SoC's devicetree,
12 &pinctrl {
17 'pinctrl' node, as shown in this example:
19 &pinctrl {
30 To link pin configurations with a device, use a pinctrl-N property for some
31 number N, like this example you could place in your board's DTS file:
33 #include "board-pinctrl.dtsi"
36 pinctrl-0 = <&uart0_default>;
37 pinctrl-names = "default";
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| D | silabs,gecko-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
10 The node has the 'pinctrl' node label set in your SoC's devicetree,
13 &pinctrl {
18 'pinctrl' node, as shown in this example:
20 /* You can put this in places like a board-pinctrl.dtsi file in
23 &pinctrl {
41 state. You would specify the low-power configuration for the same device
48 include/dt-bindings/pinctrl/gecko-pinctrl.h header file.
50 To link this pin configuration with a device, use a pinctrl-N property
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| D | renesas,ra-pincrl-pfs.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 The node has the 'pinctrl' node label set in your SoC's devicetree,
12 &pinctrl {
17 'pinctrl' node, as shown in this example:
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/renesas/pinctrl-ra.h>
26 &pinctrl {
32 drive-strength = "medium";
50 pins, such as the 'input-enable' property in group 2. Here is a list of
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| D | renesas,smartbond-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 The node has the 'pinctrl' node label set in your SoC's devicetree,
12 &pinctrl {
17 'pinctrl' node, as shown in this example:
19 /* You can put this in places like a board-pinctrl.dtsi file in
24 #include <dt-bindings/pinctrl/smartbond-pinctrl.h>
26 &pinctrl {
36 /* route UART RX to P0.8 and enable pull-up */
38 bias-pull-up;
53 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
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| D | telink,b91-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 TX to pin PB2 and enable the pull-up resistor
10 The node has the 'pinctrl' node label set in your SoC's devicetree,
13 &pinctrl {
18 'pinctrl' node, as shown in this example:
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined pins and functions for the SoC used by the board */
25 #include <dt-bindings/pinctrl/b91-pinctrl.h>
27 &pinctrl {
42 (that is, active) state. You would specify the low-power configuration for
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| D | ite,it8xxx2-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 The node has the 'pinctrl' node label set in your SoC's devicetree,
13 &pinctrl {
18 'pinctrl' node, as shown in this example:
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined pins and functions for the SoC used by the board */
25 #include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
27 &pinctrl {
31 gpio-voltage = "1p8";
35 gpio-voltage = "1v8";
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| D | atmel,sam-pinctrl.yaml | 3 # Copyright (c) 2021-2022, Gerson Fernando Budke <nandojve@gmail.com>
4 # SPDX-License-Identifier: Apache-2.0
7 Atmel SAM Pinctrl container node
11 to route USART0 RX to pin PA10 and enable the pull-up resistor on the pin.
13 The node has the 'pinctrl' node label set in your SoC's devicetree, so you can
16 &pinctrl {
20 All device pin configurations should be placed in child nodes of the 'pinctrl'
23 /** You can put this in places like a <board>-pinctrl.dtsi file in
27 /** include pre-defined combinations for the SoC variant used by the board */
28 #include <dt-bindings/pinctrl/sam4sXc-pinctrl.h>
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| D | ti,cc32xx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
10 The node has the 'pinctrl' node label set in your SoC's devicetree,
13 &pinctrl {
18 'pinctrl' node, as shown in this example:
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
27 &pinctrl {
39 /* both pin 57 and 62 have pull-up enabled */
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| D | atmel,sam0-pinctrl.yaml | 2 # Copyright (c) 2021-2022, Gerson Fernando Budke
3 # SPDX-License-Identifier: Apache-2.0
6 Atmel SAM0 Pinctrl container node
10 to route SERCOM0 as UART were RX to pin PAD1 and enable the pull-up resistor
13 The node has the 'pinctrl' node label set in your SoC's devicetree, so you can
16 &pinctrl {
20 All device pin configurations should be placed in child nodes of the 'pinctrl'
23 /** You can put this in places like a <board>-pinctrl.dtsi file in
27 /** include pre-defined combinations for the SoC variant used by the board */
28 #include <dt-bindings/pinctrl/samr21g-pinctrl.h>
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| D | nxp,s32k3-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 NXP S32 pinctrl node for S32K3 SoCs.
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
16 For example, to configure the pinmux for UART0, modify the 'pinctrl' from your
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
22 &pinctrl {
26 output-enable;
30 input-enable;
37 device can be specified in separate child nodes of 'pinctrl'.
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
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| D | renesas,rcar-pfc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Renesas R-Car Pin Function Controller node
6 This binding gives a base representation of the R-Car pins configuration.
7 The R-Car pin controller is a singleton node responsible for controlling
9 node to route CAN0 TX A to pin 'RD', and enable pull-up resistor as well
21 /* You can put this in places like a board-pinctrl.dtsi file in
25 /* include pre-defined pins and functions for the SoC used by the board */
26 #include <dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
43 (that is, active) state. You would specify the low-power configuration for
47 'bias-pull-up' property. Here is a list of supported standard pin
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| D | gd,gd32-pinctrl-af.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
10 The node has the 'pinctrl' node label set in your SoC's devicetree,
13 &pinctrl {
18 'pinctrl' node, as shown in this example:
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
27 &pinctrl {
39 /* both PA10 and PA12 have pull-up enabled */
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| D | raspberrypi,pico-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
10 The node has the 'pinctrl' node label set in your SoC's devicetree,
13 &pinctrl {
18 'pinctrl' node, as shown in this example:
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
27 &pinctrl {
40 input-enable;
54 pins, such as the 'input-enable' property in group 2. Here is a list of
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| D | nordic,nrf-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
10 The node has the 'pinctrl' node label set in your SoC's devicetree,
13 &pinctrl {
18 'pinctrl' node, as shown in this example:
20 /* You can put this in places like a board-pinctrl.dtsi file in
23 &pinctrl {
35 /* both P0.3 and P0.4 are configured with pull-up */
36 bias-pull-up;
43 state. You would specify the low-power configuration for the same device
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,flexio-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 The two PWM modes supported by flexio are chosen based on the selected polarity -
7 Dual 8-bit counters PWM mode and Dual 8-bit counters PWM Low mode.
9 compatible: "nxp,flexio-pwm"
11 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 "#pwm-cells":
23 pwm-cells:
24 - channel
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| /Zephyr-latest/dts/bindings/ospi/ |
| D | st,stm32-ospi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
16 dma-names = "tx_rx";
21 compatible: "st,stm32-ospi"
23 include: [base.yaml, pinctrl-device.yaml]
34 pinctrl-0:
37 pinctrl-names:
40 clock-names:
50 - &dma1: dma controller phandle
51 - 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
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| /Zephyr-latest/boards/st/stm32l4r9i_disco/ |
| D | stm32l4r9i_disco.dts | 4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
8 #include <st/l4/stm32l4r9a(g-i)ix-pinctrl.dtsi>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics STM32L4R9I-DISCO board";
14 compatible = "st,stm32l4r9i-disco";
18 zephyr,shell-uart = &usart2;
24 compatible = "gpio-leds";
25 /* N.B. LD1 (orange) is not wired to MCU */
33 compatible = "gpio-keys";
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| /Zephyr-latest/doc/hardware/pinctrl/ |
| D | index.rst | 1 .. _pinctrl-guide:
6 This is a high-level guide to pin control. See :ref:`pinctrl_api` for API
13 parameters such as pin direction, pull-up/down resistors, etc. are named **pin
18 of a peripheral, for example, the slew-rate depending on the operating
20 range from simple pull-up/down options to more advanced settings such as
21 debouncing, low-power modes, etc.
29 pull-up/down are controlled in the same block via ``CONFIG`` bits. This model is
32 .. figure:: images/hw-cent-control.svg
34 Example of pin control centralized into a single per-pin block
41 .. figure:: images/hw-dist-control.svg
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| /Zephyr-latest/boards/96boards/argonkey/ |
| D | 96b_argonkey.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f412c(e-g)ux-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &usart1;
24 compatible = "gpio-leds";
36 compatible = "gpio-keys";
57 clock-frequency = <DT_FREQ_M(16)>;
62 div-m = <8>;
63 mul-n = <84>;
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| /Zephyr-latest/boards/96boards/stm32_sensor_mez/ |
| D | 96b_stm32_sensor_mez.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f446v(c-e)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,stm32f446-b96b-f446ve";
18 zephyr,shell-uart = &uart4;
24 compatible = "gpio-leds";
40 compatible = "gpio-keys";
61 clock-frequency = <DT_FREQ_M(16)>;
66 div-m = <8>;
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| /Zephyr-latest/boards/st/stm32h735g_disco/ |
| D | stm32h735g_disco.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h735igkx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "st,stm32h735g-disco";
19 zephyr,shell-uart = &usart3;
26 compatible = "gpio-leds";
38 compatible = "gpio-keys";
50 volt-sensor1 = &vbat;
55 clock-frequency = <DT_FREQ_M(25)>;
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