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/Zephyr-Core-3.6.0/soc/arm/silabs_exx32/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h>
21 #include <zephyr/dt-bindings/pinctrl/gecko-pinctrl.h>
36 * @param node_id Node identifier.
45 * @param node_id Node identifier.
57 * @param pincfg Pin configuration bit field.
59 #define GECKO_GET_FUN(pincfg) (((pincfg) >> GECKO_FUN_POS) & GECKO_FUN_MSK) argument
64 * @param pincfg port configuration bit field.
66 #define GECKO_GET_PORT(pincfg) (((pincfg) >> GECKO_PORT_POS) & GECKO_PORT_MSK) argument
71 * @param pincfg pin configuration bit field.
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/Zephyr-Core-3.6.0/soc/common/nordic_nrf/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/pinctrl/nrf-pinctrl.h>
31 * @param node_id Node identifier.
47 * @param node_id Node identifier.
58 * @param pincfg Pin configuration bit field.
60 #define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK) argument
65 * @param pincfg Pin configuration bit field.
67 #define NRF_GET_INVERT(pincfg) (((pincfg) >> NRF_INVERT_POS) & NRF_INVERT_MSK) argument
72 * @param pincfg Pin configuration bit field.
74 #define NRF_GET_LP(pincfg) (((pincfg) >> NRF_LP_POS) & NRF_LP_MSK) argument
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/Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/esp32s2/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
33 * @param node_id Node identifier.
38 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
40 * @param node_id Node identifier.
56 * @param node_id Node identifier.
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
67 * @param node_id Node identifier.
/Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/esp32s3/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
35 * @param node_id Node identifier.
40 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
42 * @param node_id Node identifier.
58 * @param node_id Node identifier.
64 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
69 * @param node_id Node identifier.
/Zephyr-Core-3.6.0/soc/riscv/espressif_esp32/esp32c3/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
33 * @param node_id Node identifier.
38 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
40 * @param node_id Node identifier.
56 * @param node_id Node identifier.
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
67 * @param node_id Node identifier.
/Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/esp32/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
26 /** Pincfg settings (bias). */
27 uint32_t pincfg; member
33 * @param node_id Node identifier.
38 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
40 * @param node_id Node identifier.
56 * @param node_id Node identifier.
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
67 * @param node_id Node identifier.
/Zephyr-Core-3.6.0/soc/arm/infineon_cat1/common/
Dpinctrl_soc.h2 * Copyright (c) 2016-2017 Piotr Mienkowski
7 * SPDX-License-Identifier: Apache-2.0
54 /* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
58 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
69 * [0..7] - Port nunder
70 * [8..15] - Pin number
71 * [16..23]- HSIOM function
76 uint32_t pincfg; member
88 * @param node_id Node identifier.
93 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
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/Zephyr-Core-3.6.0/tests/drivers/pinctrl/api/src/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
39 * @name Test pinctrl pull-up/down.
43 /** Pull-up disabled. */
45 /** Pull-down enabled. */
47 /** Pull-up enabled. */
55 * @param pincfg Pin configuration bit field.
57 #define TEST_GET_PULL(pincfg) (((pincfg) >> TEST_PULL_POS) & TEST_PULL_MSK) argument
62 * @param pincfg Pin configuration bit field.
64 #define TEST_GET_PIN(pincfg) (((pincfg) >> TEST_PIN_POS) & TEST_PIN_MSK) argument
74 * @param node_id Node identifier.
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/Zephyr-Core-3.6.0/soc/arm/st_stm32/common/
Dpinctrl_soc.h5 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h>
22 #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
36 uint32_t pincfg; member
42 * @param node_id Node identifier.
60 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (F1).
62 * @param node_id Node identifier.
75 * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (non-F1).
77 * @param node_id Node identifier.
95 * @param node_id Node identifier.
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/Zephyr-Core-3.6.0/dts/bindings/test/
Dvnd,pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Test pin controller node
8 include: pincfg-node.yaml
Dvnd,pinctrl-test.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "vnd,pinctrl-test"
11 child-binding:
13 Test pin controller pin configuration nodes. Each node is composed by one or
16 child-binding:
21 /* node representing default state for test_device0 */
27 /* both pins 0 and 1 have pull-up enabled */
28 bias-pull-up;
35 /* pin M has pull-down enabled */
36 bias-pull-down;
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/Zephyr-Core-3.6.0/dts/bindings/pinctrl/
Dnxp,kinetis-pinmux.yaml1 description: Kinetis pinmux node
3 compatible: "nxp,kinetis-pinmux"
14 child-binding:
15 include: pincfg-node.yaml
Dxlnx,pinctrl-zynqmp.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Xilinx ZynqMP SoC pinctrl node. It allows configuration of pin assignments
10 compatible: "xlnx,pinctrl-zynqmp"
14 child-binding:
17 child-binding:
20 - name: pincfg-node.yaml
Dmicrochip,xec-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
6 Microchip XEC Pin controller Node
7 Based on pincfg-node.yaml binding.
8 The MCHP XEC pin controller is a singleton node responsible for controlling
10 node to select peripheral pin functions.
12 The node has the 'pinctrl' node label set in your SoC's devicetree,
20 'pinctrl' node, as in the spi0 example shown at the end:
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
26 - bias-disable: Disable pull-up/down (default behavior, not required).
27 - bias-pull-down: Enable pull-down resistor.
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Dinfineon,xmc4xxx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 The pinctrl settings are referenced in a device tree peripheral node. For example in a UART
9 node:
12 compatible = "infineon,xmc4xxx-uart";
13 pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
14 pinctrl-names = "default";
15 input-src = "DX0D";
19 pinctrl-0 is the phandle that stores the pin settings for two pins: &uart_tx_p0_1_u1c1
20 and &uart_rx_p0_0_u1c1. These nodes are pre-defined and their naming convention is designed
24 The pre-defined nodes only set the alternate function of the output pin. The
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Dcypress,psoc6-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
6 Cypress PSoC-6 Pinctrl container node
8 The Cypress PSoC-6 pins implements following pin configuration option:
10 * bias-pull-up
11 * bias-pull-down
12 * drive-open-drain
13 * drive-open-source
14 * drive-push-pull (strong)
15 * input-enable (input-buffer)
20 compatible: "cypress,psoc6-pinctrl"
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Dnuvoton,numicro-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton NuMicro pinctrl node. This node will define pin configurations in pin groups,
6 and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
19 compatible: "nuvoton,numicro-pinctrl"
27 child-binding:
29 child-binding:
31 NuMicro pin controller pin configuration node
33 - name: pincfg-node.yaml
34 property-allowlist:
35 - bias-pull-down
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Dst,stm32-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
25 remap-pa12:
30 remap-pa11-pa12:
35 child-binding:
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Dgd,gd32-pinctrl-common.yaml2 # SPDX-License-Identifier: Apache-2.0
6 child-binding:
7 child-binding:
9 - name: pincfg-node.yaml
10 property-allowlist:
11 - drive-push-pull
12 - drive-open-drain
13 - bias-disable
14 - bias-pull-down
15 - bias-pull-up
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Dst,stm32f1-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F1 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
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Dopenisa,rv32m1-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
6 OpenISA RV32M1 pinctrl node. This node will define pin configurations in pin groups,
7 and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
18 drive-strength = "low";
19 slew-rate = "fast";
28 PCR_SRE=<slew-rate selection>,
31 compatible: "openisa,rv32m1-pinctrl"
35 child-binding:
37 child-binding:
39 RV31M1 pin controller pin configuration node
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Dnuvoton,numaker-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to set UART0 RX as pin PB12 to fulfill SYS_GPB_MFP3_PB12MFP_UART0_RXD.
9 The node has the 'pinctrl' node label set in your SoC's devicetree,
17 'pinctrl' node, as shown in this example:
30 To link pin configurations with a device, use a pinctrl-N property for some
33 #include "board-pinctrl.dtsi"
36 pinctrl-0 = <&uart0_default>;
37 pinctrl-names = "default";
40 compatible: "nuvoton,numaker-pinctrl"
48 child-binding:
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/Zephyr-Core-3.6.0/include/zephyr/drivers/pinctrl/
Dpinctrl_soc_gd32_common.h4 * SPDX-License-Identifier: Apache-2.0
19 #include <dt-bindings/pinctrl/gd32-af.h>
21 #include <dt-bindings/pinctrl/gd32-afio.h>
33 * - 0-12: GD32_PINMUX_AF bit field.
34 * - 13-25: Reserved.
35 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
38 * - 0-19: GD32_PINMUX_AFIO bit field.
39 * - 20-25: Reserved.
40 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
47 * @param node_id Node identifier.
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Dpinctrl_soc_sam_common.h4 * SPDX-License-Identifier: Apache-2.0
17 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
28 * - 0-15: SAM pinmux bit field (@ref SAM_PINMUX).
29 * - 16-21: Pin flags bit field (@ref SAM_PINFLAGS).
30 * - 22-31: Reserved.
37 * @param node_id Node identifier.
62 * @param node_id Node identifier.
102 * @param pincfg pinctrl_soc_pin_t bit field value.
105 #define SAM_PINCTRL_FLAG_GET(pincfg, pos) \ argument
106 (((pincfg) >> pos) & SAM_PINCTRL_FLAG_MASK)
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/Zephyr-Core-3.6.0/soc/riscv/ite_ec/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
24 * pull-up/down, voltage selection, input.
26 uint32_t pincfg; member
41 * Pin pull-up/down config [ 4 : 5 ]
44 * Pin push-pull/open-drain [ 16 ]
56 /* Pin tri-state mode. */
59 /* Pin pull-up or pull-down */
69 /* Pin push-pull/open-drain mode */
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