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/Zephyr-latest/soc/atmel/sam/common/
Dsoc_gpio.c3 * SPDX-License-Identifier: Apache-2.0
24 static void configure_common_attr(Pio *pio, uint32_t mask, uint32_t flags) in configure_common_attr() argument
26 /* Disable interrupts on the pin(s) */ in configure_common_attr()
27 pio->PIO_IDR = mask; in configure_common_attr()
29 /* Configure pull-up(s) */ in configure_common_attr()
31 pio->PIO_PUER = mask; in configure_common_attr()
33 pio->PIO_PUDR = mask; in configure_common_attr()
36 /* Configure pull-down only for MCU series that support it */ in configure_common_attr()
38 /* Configure pull-down(s) */ in configure_common_attr()
40 pio->PIO_PPDER = mask; in configure_common_attr()
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Dsoc_sam4l_gpio.c3 * SPDX-License-Identifier: Apache-2.0
7 * @brief Atmel SAM MCU family General-Purpose Input/Output Controller (GPIO)
15 uint32_t mask, uint32_t flags) in configure_common_attr() argument
19 /* Disable interrupts on the pin(s) */ in configure_common_attr()
20 gpio->IERC = mask; in configure_common_attr()
22 /* Configure pull-up(s) */ in configure_common_attr()
24 gpio->PUERS = mask; in configure_common_attr()
26 gpio->PUERC = mask; in configure_common_attr()
29 /* Configure pull-down(s) */ in configure_common_attr()
31 gpio->PDERS = mask; in configure_common_attr()
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Dsoc_gpio.h2 * Copyright (c) 2016-2017 Piotr Mienkowski
4 * SPDX-License-Identifier: Apache-2.0
19 * Pin flags/attributes
22 /* TODO: replace hard coded pin attribute values with defines provided
62 /** Connect pin to peripheral A. */
64 /** Connect pin to peripheral B. */
66 /** Connect pin to peripheral C. */
68 /** Connect pin to peripheral D. */
70 /** Connect pin to peripheral E. */
72 /** Connect pin to peripheral F. */
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/Zephyr-latest/drivers/gpio/
Dgpio_mmio32.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Driver to provide the GPIO API for a simple 32-bit i/o register
11 * This is a driver for accessing a simple, fixed purpose, 32-bit
12 * memory-mapped i/o register using the same APIs as GPIO drivers. This is
15 * expects to be specified using a GPIO pin, e.g. for driving an LED, or
16 * chip-select line for an SPI device.
21 * stems from the use of a read-modify-write method for all changes.
23 * It is possible to specify a restricted mask of bits that are valid for
25 * mask will be preserved, even when the whole port is written to using
34 gpio_pin_t pin, gpio_flags_t flags) in gpio_mmio32_config() argument
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Dgpio_npcx.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/gpio/nuvoton-npcx-gpio.h>
50 ((struct gpio_reg *)((const struct gpio_npcx_config *)(dev)->config)->base)
62 void npcx_gpio_enable_io_pads(const struct device *dev, int pin) in npcx_gpio_enable_io_pads() argument
64 const struct gpio_npcx_config *const config = dev->config; in npcx_gpio_enable_io_pads()
65 const struct npcx_wui *io_wui = &config->wui_maps[pin]; in npcx_gpio_enable_io_pads()
67 if (io_wui->table == NPCX_MIWU_TABLE_NONE) { in npcx_gpio_enable_io_pads()
68 LOG_ERR("Cannot enable GPIO(%x, %d) pad", config->port, pin); in npcx_gpio_enable_io_pads()
73 * If this pin is configured as a GPIO interrupt source, do not in npcx_gpio_enable_io_pads()
76 if (pin < NPCX_GPIO_PORT_PIN_NUM && !npcx_miwu_irq_get_state(io_wui)) { in npcx_gpio_enable_io_pads()
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Dgpio_stellaris.c4 * SPDX-License-Identifier: Apache-2.0
39 #define GPIO_RW_MASK_ADDR(base, offset, mask) \ argument
40 (GPIO_REG_ADDR(base, offset) | (mask << 2))
56 const struct gpio_stellaris_config * const cfg = dev->config; in gpio_stellaris_isr()
57 struct gpio_stellaris_runtime *context = dev->data; in gpio_stellaris_isr()
58 uint32_t base = cfg->base; in gpio_stellaris_isr()
61 gpio_fire_callbacks(&context->cb, dev, int_stat); in gpio_stellaris_isr()
67 gpio_pin_t pin, gpio_flags_t flags) in gpio_stellaris_configure() argument
69 const struct gpio_stellaris_config *cfg = dev->config; in gpio_stellaris_configure()
70 uint32_t base = cfg->base; in gpio_stellaris_configure()
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Dgpio_tle9104.c4 * SPDX-License-Identifier: Apache-2.0
39 static int tle9104_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in tle9104_gpio_pin_configure() argument
41 const struct tle9104_gpio_config *config = dev->config; in tle9104_gpio_pin_configure()
42 struct tle9104_gpio_data *data = dev->data; in tle9104_gpio_pin_configure()
47 return -EWOULDBLOCK; in tle9104_gpio_pin_configure()
50 if (pin >= TLE9104_GPIO_COUNT) { in tle9104_gpio_pin_configure()
51 LOG_ERR("invalid pin number %i", pin); in tle9104_gpio_pin_configure()
52 return -EINVAL; in tle9104_gpio_pin_configure()
56 LOG_ERR("cannot configure pin as input"); in tle9104_gpio_pin_configure()
57 return -ENOTSUP; in tle9104_gpio_pin_configure()
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Dgpio_emul.c4 * SPDX-License-Identifier: Apache-2.0
55 * Pin direction as well as other pin properties are set using
87 /** Input values for each pin */
89 /** Output values for each pin */
91 /** Interrupt status for each pin */
95 /** Is interrupt enabled for each pin */
97 /** Singly-linked list of callbacks associated with the controller */
102 * @brief Obtain a mask of pins that match all of the provided @p flags
109 * @param mask A mask of flags to match
112 * @return a mask of the pins with matching @p flags
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Dgpio_cc13xx_cc26xx.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h>
29 /* bits 16-18 in iocfg registers correspond to interrupt settings */
32 /* the rest are for general (non-interrupt) config */
48 uint32_t mask);
50 uint32_t mask);
53 gpio_pin_t pin, in gpio_cc13xx_cc26xx_config() argument
58 __ASSERT_NO_MSG(pin < NUM_IO_MAX); in gpio_cc13xx_cc26xx_config()
68 IOCPortConfigureSet(pin, IOC_PORT_GPIO, IOC_NO_IOPULL); in gpio_cc13xx_cc26xx_config()
69 GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE); in gpio_cc13xx_cc26xx_config()
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Dgpio_bd8lb600fs.c5 * SPDX-License-Identifier: Apache-2.0
37 static int bd8lb600fs_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, in bd8lb600fs_gpio_pin_configure() argument
40 const struct bd8lb600fs_gpio_config *config = dev->config; in bd8lb600fs_gpio_pin_configure()
41 struct bd8lb600fs_gpio_data *data = dev->data; in bd8lb600fs_gpio_pin_configure()
45 return -EWOULDBLOCK; in bd8lb600fs_gpio_pin_configure()
48 if (pin >= config->gpios_count) { in bd8lb600fs_gpio_pin_configure()
49 LOG_ERR("invalid pin number %i", pin); in bd8lb600fs_gpio_pin_configure()
50 return -EINVAL; in bd8lb600fs_gpio_pin_configure()
54 LOG_ERR("cannot configure pin as input"); in bd8lb600fs_gpio_pin_configure()
55 return -ENOTSUP; in bd8lb600fs_gpio_pin_configure()
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Dgpio_xlnx_ps_bank.c6 * SPDX-License-Identifier: Apache-2.0
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
28 * @brief GPIO bank pin configuration function
30 * Configures an individual pin within a MIO / EMIO GPIO pin bank.
34 * - Pull up
35 * - Pull down
36 * - Open drain
37 * - Open source.
40 * @param pin Index of the pin within the bank to be configured
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Dgpio_nrfx.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h>
41 return port->data; in get_port_data()
46 return port->config; in get_port_cfg()
51 return cfg->gpiote.p_reg != NULL; in has_gpiote()
65 static int gpio_nrfx_gpd_retain_set(const struct device *port, uint32_t mask, gpio_flags_t flags) in gpio_nrfx_gpd_retain_set() argument
70 if (cfg->pad_pd == NRF_GPD_FAST_ACTIVE1) { in gpio_nrfx_gpd_retain_set()
74 nrf_gpio_port_retain_enable(cfg->port, mask); in gpio_nrfx_gpd_retain_set()
84 ARG_UNUSED(mask); in gpio_nrfx_gpd_retain_set()
91 static int gpio_nrfx_gpd_retain_clear(const struct device *port, uint32_t mask) in gpio_nrfx_gpd_retain_clear() argument
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Dgpio_cmsdk_ahb.c4 * SPDX-License-Identifier: Apache-2.0
51 const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config; in gpio_cmsdk_ahb_port_get_raw()
53 *value = cfg->port->data; in gpio_cmsdk_ahb_port_get_raw()
59 uint32_t mask, in gpio_cmsdk_ahb_port_set_masked_raw() argument
62 const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config; in gpio_cmsdk_ahb_port_set_masked_raw()
64 cfg->port->dataout = (cfg->port->dataout & ~mask) | (mask & value); in gpio_cmsdk_ahb_port_set_masked_raw()
70 uint32_t mask) in gpio_cmsdk_ahb_port_set_bits_raw() argument
72 const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config; in gpio_cmsdk_ahb_port_set_bits_raw()
74 cfg->port->dataout |= mask; in gpio_cmsdk_ahb_port_set_bits_raw()
80 uint32_t mask) in gpio_cmsdk_ahb_port_clear_bits_raw() argument
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Dgpio_sam.c5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/gpio/atmel-sam-gpio.h>
41 static int gpio_sam_port_configure(const struct device *dev, uint32_t mask, in gpio_sam_port_configure() argument
44 const struct gpio_sam_config * const cfg = dev->config; in gpio_sam_port_configure()
45 Pio * const pio = cfg->regs; in gpio_sam_port_configure()
49 /* Enable open-drain drive mode */ in gpio_sam_port_configure()
50 pio->PIO_MDER = mask; in gpio_sam_port_configure()
52 /* Open-drain is the only supported single-ended mode */ in gpio_sam_port_configure()
53 return -ENOTSUP; in gpio_sam_port_configure()
56 /* Disable open-drain drive mode */ in gpio_sam_port_configure()
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Dgpio_rv32m1.c6 * SPDX-License-Identifier: Apache-2.0
41 uint32_t pin, in get_port_pcr_irqc_value_from_flags() argument
68 return -EINVAL; in get_port_pcr_irqc_value_from_flags()
77 gpio_pin_t pin, gpio_flags_t flags) in gpio_rv32m1_configure() argument
79 const struct gpio_rv32m1_config *config = dev->config; in gpio_rv32m1_configure()
80 GPIO_Type *gpio_base = config->gpio_base; in gpio_rv32m1_configure()
81 PORT_Type *port_base = config->port_base; in gpio_rv32m1_configure()
82 uint32_t mask = 0U; in gpio_rv32m1_configure() local
85 /* Check for an invalid pin number */ in gpio_rv32m1_configure()
86 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_rv32m1_configure()
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Dgpio_iproc.c5 * SPDX-License-Identifier: Apache-2.0
43 #define DEV_CFG(dev) ((const struct gpio_iproc_config *const)(dev)->config)
44 #define DEV_DATA(dev) ((struct gpio_iproc_data *const)(dev)->data)
46 static int gpio_iproc_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in gpio_iproc_configure() argument
49 mem_addr_t base = cfg->base; in gpio_iproc_configure()
51 /* Setup the pin direcion. */ in gpio_iproc_configure()
53 /* configure pin for output */ in gpio_iproc_configure()
54 sys_set_bit(base + IPROC_GPIO_OUT_EN_OFFSET, pin); in gpio_iproc_configure()
56 /* configure pin for input */ in gpio_iproc_configure()
57 sys_clear_bit(base + IPROC_GPIO_OUT_EN_OFFSET, pin); in gpio_iproc_configure()
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Dgpio_kscan_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
21 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio output enable register (bit mapping to pin) */
23 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register (bit mapping to pin) */
25 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data register (bit mapping to pin) */
27 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data mirror register (bit mapping to pin) */
29 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio open drain register (bit mapping to pin) */
39 gpio_pin_t pin, in gpio_kscan_it8xxx2_configure() argument
42 const struct gpio_kscan_cfg *const config = dev->config; in gpio_kscan_it8xxx2_configure()
43 volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl; in gpio_kscan_it8xxx2_configure()
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Dgpio_grgpio2.c4 * SPDX-License-Identifier: Apache-2.0
9 * - iflag determine pending interrupt.
10 * - interrupt map decides interrupt number if implemented.
11 * - logic or/and/xor registers used when possible
43 gpio_pin_t pin, gpio_flags_t flags) in pin_configure() argument
45 const struct cfg *cfg = dev->config; in pin_configure()
46 struct data *data = dev->data; in pin_configure()
47 volatile struct grgpio_regs *regs = cfg->regs; in pin_configure()
48 uint32_t mask = 1 << pin; in pin_configure() local
51 return -ENOTSUP; in pin_configure()
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Dgpio_nct38xx_port.c4 * SPDX-License-Identifier: Apache-2.0
24 /* GPIO port 0 pinmux mask */
41 static int gpio_nct38xx_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in gpio_nct38xx_pin_config() argument
43 const struct gpio_nct38xx_port_config *const config = dev->config; in gpio_nct38xx_pin_config()
44 struct gpio_nct38xx_port_data *const data = dev->data; in gpio_nct38xx_pin_config()
45 uint32_t mask; in gpio_nct38xx_pin_config() local
51 return -ENOTSUP; in gpio_nct38xx_pin_config()
56 return -ENOTSUP; in gpio_nct38xx_pin_config()
59 /* Don't support pull-up/pull-down */ in gpio_nct38xx_pin_config()
61 return -ENOTSUP; in gpio_nct38xx_pin_config()
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Dgpio_cc32xx.c4 * SPDX-License-Identifier: Apache-2.0
22 #include <driverlib/pin.h>
64 uint32_t mask);
66 uint32_t mask);
69 gpio_pin_t pin, in gpio_cc32xx_config() argument
72 const struct gpio_cc32xx_config *gpio_config = port->config; in gpio_cc32xx_config()
73 unsigned long port_base = gpio_config->port_base; in gpio_cc32xx_config()
76 return -ENOTSUP; in gpio_cc32xx_config()
80 return -ENOTSUP; in gpio_cc32xx_config()
84 return -ENOTSUP; in gpio_cc32xx_config()
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Dgpio_mchp_mss.c4 * SPDX-License-Identifier: Apache-2.0
63 ((const struct mss_gpio_config * const)(dev)->config)
65 ((volatile struct mss_gpio_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
67 ((struct mss_gpio_data *)(dev)->data)
71 gpio_pin_t pin, in mss_gpio_config() argument
79 return -ENOTSUP; in mss_gpio_config()
84 gpio->gpio_cfg[pin] |= MSS_GPIO_OUTPUT_MODE; in mss_gpio_config()
87 gpio->gpio_out |= BIT(pin); in mss_gpio_config()
90 gpio->gpio_out &= ~BIT(pin); in mss_gpio_config()
95 gpio->gpio_cfg[pin] |= MSS_GPIO_INPUT_MODE; in mss_gpio_config()
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Dgpio_numicro.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/numicro-gpio.h>
19 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
21 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
22 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
23 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
24 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
50 gpio_pin_t pin, gpio_flags_t flags) in gpio_numicro_configure() argument
52 const struct gpio_numicro_config *cfg = dev->config; in gpio_numicro_configure()
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/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dwuc_ite_it8xxx2.h4 * SPDX-License-Identifier: Apache-2.0
15 * a wake-up signal to the power management control of EC
18 * @param mask Pin mask of WUC group
20 void it8xxx2_wuc_enable(const struct device *dev, uint8_t mask);
24 * assert the wake-up signal (canceled not pending)
27 * @param mask Pin mask of WUC group
29 void it8xxx2_wuc_disable(const struct device *dev, uint8_t mask);
32 * @brief Write-1-clear a trigger condition that occurs on the
36 * @param mask Pin mask of WUC group
38 void it8xxx2_wuc_clear_status(const struct device *dev, uint8_t mask);
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_sam0_eic.c4 * SPDX-License-Identifier: Apache-2.0
16 uint8_t pin : 5; member
34 while (EIC->SYNCBUSY.reg) { in wait_synchronization()
37 while (EIC->STATUS.bit.SYNCBUSY) { in wait_synchronization()
45 EIC->CTRLA.bit.ENABLE = on; in set_eic_enable()
47 EIC->CTRL.bit.ENABLE = on; in set_eic_enable()
53 struct sam0_eic_data *const dev_data = dev->data; in sam0_eic_isr()
54 uint16_t bits = EIC->INTFLAG.reg; in sam0_eic_isr()
58 EIC->INTFLAG.reg = bits; in sam0_eic_isr()
74 * Map the EIC lines to the port pin masks based on which port is in sam0_eic_isr()
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/Zephyr-latest/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8XXX2 pin controller function node
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
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