6  * SPDX-License-Identifier: Apache-2.0
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
28  * @brief GPIO bank pin configuration function
30  * Configures an individual pin within a MIO / EMIO GPIO pin bank.
34  * - Pull up
35  * - Pull down
36  * - Open drain
37  * - Open source.
40  * @param pin Index of the pin within the bank to be configured
41  *            (decimal index of the pin).
42  * @param flags Flags specifying the pin's configuration.
45  *         -EINVAL if the specified pin index is out of range,
46  *         -ENOTSUP if the pin configuration data contains a flag
50 				      gpio_pin_t pin,  in gpio_xlnx_ps_pin_configure()  argument
55 	uint32_t pin_mask = BIT(pin);  in gpio_xlnx_ps_pin_configure()
60 	/* Validity of the specified pin index is checked in drivers/gpio.h */  in gpio_xlnx_ps_pin_configure()
64 		return -ENOTSUP;  in gpio_xlnx_ps_pin_configure()
85 		 * If the current pin is to be configured as an output  in gpio_xlnx_ps_pin_configure()
86 		 * pin, it is up to the caller to specify whether the  in gpio_xlnx_ps_pin_configure()
88 		 * -> Write the initial output value into the data register.  in gpio_xlnx_ps_pin_configure()
98 		/* Set the pin's output enable bit */  in gpio_xlnx_ps_pin_configure()
105 		 * Disable the output first in case of an O -> I  in gpio_xlnx_ps_pin_configure()
106 		 * transition, then change the pin's direction.  in gpio_xlnx_ps_pin_configure()
116  * @brief Reads the current bit mask of the entire GPIO pin bank.
118  * Reads the current bit mask of the entire bank from the
119  * read-only data register. This includes the current values
125  *              to which the current bit mask read from the bank's
129  *         -EINVAL if the pointer to the output variable is NULL.
142  * @brief Masked write of a bit mask for the entire GPIO pin bank.
145  * the current GPIO pin bank. The mask is applied twice:
148  * mask (will not have any effect on input pins). Second, it
155  * @param mask  Mask to be applied to both the current contents
164 					gpio_port_pins_t mask,  in gpio_xlnx_ps_bank_set_masked()  argument
172 	bank_data = (bank_data & ~mask) | (value & mask);  in gpio_xlnx_ps_bank_set_masked()
179  * @brief Sets bits in the data register of the GPIO pin bank.
181  * Sets bits in the data register of the current GPIO pin bank
182  * as a read-modify-write operation. All bits set in the bit
183  * mask provided by the caller are OR'ed into the current data
188  * @param pins  Bit mask specifying which bits shall be set in
189  *              the data word of the current GPIO pin bank.
208  * @brief Clears bits in the data register of the GPIO pin bank.
210  * Clears bits in the data register of the current GPIO pin bank
211  * as a read-modify-write operation. All bits set in the bit
212  * mask provided by the caller are NAND'ed into the current data
217  * @param pins  Bit mask specifying which bits shall be cleared
218  *              in the data word of the current GPIO pin bank.
237  * @brief Toggles bits in the data register of the GPIO pin bank.
239  * Toggles bits in the data register of the current GPIO pin bank
240  * as a read-modify-write operation. All bits set in the bit
241  * mask provided by the caller are XOR'ed into the current data
246  * @param pins  Bit mask specifying which bits shall be toggled
247  *              in the data word of the current GPIO pin bank.
266  * @brief Configures the interrupt behaviour of a pin within the
269  * Configures the interrupt behaviour of a pin within the current
270  * GPIO bank. If a pin is to be configured to trigger an interrupt,
273  * - edge or level triggered,
274  * - rising edge / high level or falling edge / low level,
275  * - in edge mode only: trigger on both rising and falling edge.
278  * @param pin  Index of the pin within the bank to be configured
279  *             (decimal index of the pin).
285  *         -EINVAL if the specified pin index is out of range,
286  *         -ENOTSUP if the interrupt configuration data contains an
290 					       gpio_pin_t pin,  in gpio_xlnx_ps_bank_pin_irq_configure()  argument
296 	uint32_t pin_mask = BIT(pin);  in gpio_xlnx_ps_bank_pin_irq_configure()
301 	/* Validity of the specified pin index is checked in drivers/gpio.h */  in gpio_xlnx_ps_bank_pin_irq_configure()
303 	/* Disable the specified pin's interrupt before (re-)configuring it */  in gpio_xlnx_ps_bank_pin_irq_configure()
317 			return -EINVAL;  in gpio_xlnx_ps_bank_pin_irq_configure()
328 				return -EINVAL;  in gpio_xlnx_ps_bank_pin_irq_configure()
356  * form of a bit mask where each pin with a pending interrupt is
357  * indicated. This information can either be used by the PM sub-
360  * of how many bank sub-devices exist. As the current status is
366  * @retval A bit mask indicating for which pins within the bank
384  * @brief Callback management re-direction function.
386  * Re-directs any callback management calls relating to the current
387  * GPIO bank to the GPIO sub-system. Comp. documentation of the
388  * underlying sub-system's #gpio_manage_callback function.
394  * @retval A bit mask indicating for which pins within the bank
403 	return gpio_manage_callback(&dev_data->callbacks, callback, set);  in gpio_xlnx_ps_bank_manage_callback()
420  * @brief Initialize a MIO / EMIO GPIO bank sub-device
422  * Initialize a MIO / EMIO GPIO bank sub-device, which is a child
423  * of the parent Xilinx PS GPIO controller device driver. This ini-
436 	__ASSERT(dev_data->base != 0, "%s mapped base address missing", dev->name);  in gpio_xlnx_ps_bank_init()
437 	if (dev_data->base == 0) {  in gpio_xlnx_ps_bank_init()
438 		LOG_ERR("%s mapped base address missing", dev->name);  in gpio_xlnx_ps_bank_init()
439 		return -EIO;  in gpio_xlnx_ps_bank_init()