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/Zephyr-latest/dts/bindings/display/
Drenesas,ra-glcdc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-glcdc"
8 include: [display-controller.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
26 interrupt-names:
27 type: string-array
31 backlight-gpios:
32 type: phandle-array
36 The sensor receives this as an active-high signal.
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Dsitronix,st7796s.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
12 type: uint8-array
19 type: uint8-array
26 type: uint8-array
33 type: uint8-array
40 type: uint8-array
47 type: uint8-array
69 type: uint8-array
72 Display output control adjust. Sets display timing controls
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/Zephyr-latest/include/zephyr/drivers/
Dvideo.h10 * SPDX-License-Identifier: Apache-2.0
38 #define LINE_COUNT_HEIGHT (-1)
42 * @brief Video format structure
44 * Used to configure frame format.
47 /** FourCC pixel format value (\ref video_pixel_formats) */
57 * first pixel of a row in order to go to the address of the first pixel of
65 * @brief Video format capability
67 * Used to describe a video endpoint format capability.
70 /** FourCC pixel format value (\ref video_pixel_formats). */
88 * @brief Video format capabilities
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/Zephyr-latest/boards/shields/rtkmipilcdb00000be/
Drtkmipilcdb00000be.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 compatible = "zephyr,lvgl-pointer-input";
22 gt911_rtkmipilcdb00000be: gt911-rtkmipilcdb00000be@5d {
25 irq-gpios = <&renesas_mipi_connector 17 GPIO_ACTIVE_HIGH>;
26 reset-gpios = <&renesas_mipi_connector 18 GPIO_ACTIVE_LOW>;
34 compatible = "ilitek,ili9806e-dsi";
38 data-lanes = <2>;
39 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
47 input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
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/Zephyr-latest/tests/drivers/build_all/display/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
13 #include <zephyr/dt-bindings/led/led.h>
14 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
23 gpio-controller;
25 #gpio-cells = <0x2>;
30 compatible = "zephyr,mipi-dbi-spi";
32 dc-gpios = <&test_gpio 0 0>;
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/Zephyr-latest/drivers/display/
Ddisplay_st7796s.c4 * SPDX-License-Identifier: Apache-2.0
45 uint8_t doca[8]; /* Display output ctrl */
57 const struct st7796s_config *config = dev->config; in st7796s_send_cmd()
59 return mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config, in st7796s_send_cmd()
72 addr_data[1] = sys_cpu_to_be16(x + width - 1); in st7796s_set_cursor()
82 addr_data[1] = sys_cpu_to_be16(y + height - 1); in st7796s_set_cursor()
100 const struct st7796s_config *config = dev->config; in st7796s_get_pixelfmt()
103 * Invert the pixel format for 8-bit 8080 Parallel Interface. in st7796s_get_pixelfmt()
105 * Zephyr uses big endian byte order when the pixel format has in st7796s_get_pixelfmt()
111 * This is not an issue when using a 16-bit interface. in st7796s_get_pixelfmt()
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Ddisplay_st7796s.h4 * SPDX-License-Identifier: Apache-2.0
21 #define ST7796S_CMD_COLMOD 0x3A /* Interface pixel format */
34 #define ST7796S_CMD_DOCA 0xE8 /* Display output control adjust */
Ddisplay_ili9xxx.c6 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/display/ili9xxx.h>
70 const struct ili9xxx_config *config = dev->config; in ili9xxx_transmit()
72 return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, in ili9xxx_transmit()
92 const struct ili9xxx_config *config = dev->config; in ili9xxx_hw_reset()
94 if (mipi_dbi_reset(config->mipi_dev, ILI9XXX_RESET_PULSE_TIME) < 0) { in ili9xxx_hw_reset()
108 spi_data[1] = sys_cpu_to_be16(x + w - 1U); in ili9xxx_set_mem_area()
115 spi_data[1] = sys_cpu_to_be16(y + h - 1U); in ili9xxx_set_mem_area()
129 const struct ili9xxx_config *config = dev->config; in ili9xxx_write()
130 struct ili9xxx_data *data = dev->data; in ili9xxx_write()
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Ddisplay_renesas_lcdc.c4 * SPDX-License-Identifier: Apache-2.0
96 /* Pixel size in bytes */
104 if (atomic_test_and_set_bit(data->pm_policy_state_flag, 0) == 0) { in lcdc_smartbond_pm_policy_state_lock_get()
117 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, 0) == 1) { in lcdc_smartbond_pm_policy_state_lock_put()
124 /* Display pixel to layer color format translation */
133 LOG_ERR("Unsupported pixel format"); in lcdc_smartbond_pixel_to_lcm()
143 const struct display_smartbond_config *config = dev->config; in display_smartbond_configure()
144 struct display_smartbond_data *data = dev->data; in display_smartbond_configure()
154 return -EINVAL; in display_smartbond_configure()
157 da1469x_lcdc_parallel_interface_configure((lcdc_smartbond_mode_cfg *)&config->mode); in display_smartbond_configure()
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Ddisplay_renesas_ra.c4 * SPDX-License-Identifier: Apache-2.0
47 struct display_ra_data *data = dev->data; in renesas_ra_glcdc_isr()
50 if (data->front_buf != data->pend_buf) { in renesas_ra_glcdc_isr()
51 data->front_buf = data->pend_buf; in renesas_ra_glcdc_isr()
52 k_sem_give(&data->sem); in renesas_ra_glcdc_isr()
59 struct display_ra_data *data = dev->data; in ra_display_write()
60 const struct display_ra_config *config = dev->config; in ra_display_write()
67 __ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width"); in ra_display_write()
68 __ASSERT((desc->pitch * BYTE_PER_PIXEL * desc->height) <= desc->buf_size, in ra_display_write()
71 if (x == 0 && y == 0 && desc->height == DISPLAY_VSIZE && desc->width == DISPLAY_HSIZE && in ra_display_write()
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Dssd1322.c4 * SPDX-License-Identifier: Apache-2.0
69 const struct ssd1322_config *config = dev->config; in ssd1322_write_command()
71 return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, buf, len); in ssd1322_write_command()
85 * The controller uses 4-bit grayscale format, so one pixel is represented by 4 bits.
86 * Zephyr's display API does not support this format, so this uses mono01, and converts each 1-bit
87 * pixel to 1111 or 0000.
89 * buf_in: pointer to input buffer in mono01 format. This value will bel updated to point to
90 * the first byte after the last converted pixel.
99 /* Output buffer size gets rounded down to avoid splitting chunks in the middle of input in ssd1322_conv_mono01_grayscale()
122 *pixel_count -= pixels_in_chunk; in ssd1322_conv_mono01_grayscale()
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Ddisplay_mcux_elcdif.c2 * Copyright 2019-24, NXP
5 * SPDX-License-Identifier: Apache-2.0
68 k_sem_give(&data->pxp_done); in mcux_elcdif_pxp_callback()
75 const struct mcux_elcdif_config *config = dev->config; in mcux_elcdif_write()
76 struct mcux_elcdif_data *dev_data = dev->data; in mcux_elcdif_write()
83 __ASSERT((dev_data->pixel_bytes * desc->pitch * desc->height) <= desc->buf_size, in mcux_elcdif_write()
86 LOG_DBG("W=%d, H=%d, @%d,%d", desc->width, desc->height, x, y); in mcux_elcdif_write()
88 if ((x == 0) && (y == 0) && (desc->width == config->rgb_mode.panelWidth) && in mcux_elcdif_write()
89 (desc->height == config->rgb_mode.panelHeight) && (desc->pitch == desc->width)) { in mcux_elcdif_write()
91 LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb, (void *)buf); in mcux_elcdif_write()
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/Zephyr-latest/drivers/video/
Dvideo_mcux_csi.c5 * SPDX-License-Identifier: Apache-2.0
39 const struct device *dev = data->dev; in __frame_done_cb()
40 const struct video_mcux_csi_config *config = dev->config; in __frame_done_cb()
51 status = CSI_TransferGetFullBuffer(config->base, &(data->csi_handle), &buffer_addr); in __frame_done_cb()
58 while ((vbuf = k_fifo_get(&data->fifo_in, K_NO_WAIT))) { in __frame_done_cb()
59 if ((uint32_t)vbuf->buffer == buffer_addr) { in __frame_done_cb()
67 k_fifo_put(&data->fifo_in, vbuf); in __frame_done_cb()
83 vbuf->timestamp = k_uptime_get_32(); in __frame_done_cb()
86 DCACHE_InvalidateByRange(buffer_addr, vbuf->bytesused); in __frame_done_cb()
89 k_fifo_put(&data->fifo_out, vbuf); in __frame_done_cb()
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Dmt9m114.c5 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/video-controls.h>
54 /* Camera output format */
88 {0x316A, 2, 0x8270}, /* Auto txlo_row for hot pixel and linear full well optimization */
89 {0x316C, 2, 0x8270}, /* Auto txlo for hot pixel and linear full well optimization */
117 {0xC984, 2, 0x8000}, /* CAM_PORT_OUTPUT_CONTROL, for MIPI CSI-2 interface : 0x8000 */
174 #define MT9M114_VIDEO_FORMAT_CAP(width, height, format) \ argument
176 .pixelformat = (format), .width_min = (width), .width_max = (width), \
221 const struct mt9m114_config *cfg = dev->config; in mt9m114_write_reg()
233 return -ENOTSUP; in mt9m114_write_reg()
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Dov7670.c4 * SPDX-License-Identifier: Apache-2.0
185 #define OV7670_VIDEO_FORMAT_CAP(width, height, format) \ argument
187 .pixelformat = (format), .width_min = (width), .width_max = (width), \
209 /* configure the output timing */
210 /* PCLK does not toggle during horizontal blank, one PCLK, one pixel */
213 /* Brightness Control, with signal -128 to +128, 0x00 is middle value */
216 /* Internal clock pre-scalar,F(internal clock) = F(input clock)/(Bit[5:0]+1) */
223 /* Output Drive Capability */
224 {OV7670_COM2, 0x00}, /* Common Control 2, Output Drive Capability: 1x */
233 {OV7670_DNSTH, 0x00}, /* De-noise Strength */
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Dov7725.c4 * SPDX-License-Identifier: Apache-2.0
238 /*Output config*/
378 const struct ov7725_config *cfg = dev->config; in ov7725_write_all()
383 err = ov7725_write_reg(&cfg->i2c, regs[i].addr, regs[i].value); in ov7725_write_all()
396 const struct ov7725_config *cfg = dev->config; in ov7725_set_clock()
401 ov7725_write_reg(&cfg->i2c, OV7725_CLKRC, in ov7725_set_clock()
403 ov7725_modify_reg(&cfg->i2c, OV7725_COM4, 0xc0, in ov7725_set_clock()
405 ov7725_write_reg(&cfg->i2c, OV7725_EXHCL, 0x00); in ov7725_set_clock()
406 ov7725_write_reg(&cfg->i2c, OV7725_DM_LNL, in ov7725_set_clock()
408 ov7725_write_reg(&cfg->i2c, OV7725_DM_LNH, 0x00); in ov7725_set_clock()
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/Zephyr-latest/drivers/led_strip/
Dtlc5971.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/led/led.h>
43 * The TLC5971 has 4x RGB outputs per device, where each RGB group constitues a pixel from this
57 /** GS reference clock edge select bit for OUTXn on-off timing control in FC data */
60 /** Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). */
157 temp = pixel_data->r; in tlc5971_map_color()
160 temp = pixel_data->g; in tlc5971_map_color()
163 temp = pixel_data->b; in tlc5971_map_color()
174 * @brief serialize control data and pixel data for device daisy chain
180 * @param pixels pixel RGB data for daisy chain
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/Zephyr-latest/boards/shields/seeed_xiao_round_display/
Dseeed_xiao_round_display.overlay4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
17 compatible = "voltage-divider";
18 io-channels = <&xiao_adc 0>;
19 output-ohms = <470000>;
20 full-ohms = <940000>;
24 compatible = "zephyr,lvgl-pointer-input";
33 compatible = "zephyr,mipi-dbi-spi";
34 spi-dev = <&xiao_spi>;
35 dc-gpios = <&xiao_d 3 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/drivers/mipi_dsi/
Ddsi_mcux_2l.c4 * SPDX-License-Identifier: Apache-2.0
71 const struct mcux_mipi_dsi_config *config = dev->config; in dsi_mcux_dma_cb()
72 struct mcux_mipi_dsi_data *data = dev->data; in dsi_mcux_dma_cb()
79 DSI_DisableInterrupts(config->base, kDSI_InterruptGroup1ApbTxDone | in dsi_mcux_dma_cb()
81 DSI_GetAndClearInterruptStatus(config->base, &int_flags1, &int_flags2); in dsi_mcux_dma_cb()
82 k_sem_give(&data->transfer_sem); in dsi_mcux_dma_cb()
96 * frameworks store RGB data in little endian format, but many in dsi_mcux_tx_color()
97 * MIPI displays expect color data in big endian format. in dsi_mcux_tx_color()
99 const struct mcux_mipi_dsi_config *config = dev->config; in dsi_mcux_tx_color()
100 struct mcux_mipi_dsi_data *data = dev->data; in dsi_mcux_tx_color()
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/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
100 struct mipi_dbi_smartbond_data *data = dev->data; in mipi_dbi_smartbond_send_single_frame()
108 k_sem_take(&data->sync_sem, K_FOREVER); in mipi_dbi_smartbond_send_single_frame()
111 LCDC->LCDC_INTERRUPT_REG |= LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk; in mipi_dbi_smartbond_send_single_frame()
113 /* Setting this bit will enable the host to start outputing pixel data */ in mipi_dbi_smartbond_send_single_frame()
114 LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Msk; in mipi_dbi_smartbond_send_single_frame()
117 k_sem_take(&data->sync_sem, K_FOREVER); in mipi_dbi_smartbond_send_single_frame()
119 if (data->underflow_flag) { in mipi_dbi_smartbond_send_single_frame()
121 data->underflow_flag = false; in mipi_dbi_smartbond_send_single_frame()
128 const struct mipi_dbi_smartbond_config *config = dev->config; in mipi_dbi_smartbond_reset()
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/Zephyr-latest/boards/hardkernel/odroid_go/
Dodroid_go_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "odroid_go-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "ODROID-GO Game Kit PROCPU";
20 zephyr,shell-uart = &uart0;
22 zephyr,code-partition = &slot0_partition;
24 zephyr,bt-hci = &esp32_bt_hci;
28 compatible = "gpio-leds";
36 compatible = "gpio-keys";
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/Zephyr-latest/boards/m5stack/m5stack_core2/
Dm5stack_core2_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "m5stack_core2-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/display/ili9xxx.h>
13 #include <zephyr/dt-bindings/regulator/axp192.h>
21 pwr-led = &pwr_led;
22 uart-0 = &uart0;
23 i2c-0 = &i2c0;
33 zephyr,shell-uart = &uart0;
36 zephyr,code-partition = &slot0_partition;
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/Zephyr-latest/boards/espressif/esp_wrover_kit/
Desp_wrover_kit_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "esp_wrover_kit-pinctrl.dtsi"
13 model = "Espressif ESP32-Wrover-Kit PROCPU";
20 pwm-led0 = &pwm_led_red;
21 pwm-led1 = &pwm_led_green;
22 pwm-led2 = &pwm_led_blue;
23 red-pwm-led = &pwm_led_red;
24 green-pwm-led = &pwm_led_green;
25 blue-pwm-led = &pwm_led_blue;
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/Zephyr-latest/drivers/dma/
Ddma_mcux_pxp.c2 * Copyright 2023-2024 NXP
5 * SPDX-License-Identifier: Apache-2.0
38 const struct dma_mcux_pxp_config *config = dev->config; in dma_mcux_pxp_irq_handler()
39 struct dma_mcux_pxp_data *data = dev->data; in dma_mcux_pxp_irq_handler()
41 PXP_ClearStatusFlags(config->base, kPXP_CompleteFlag); in dma_mcux_pxp_irq_handler()
43 DCACHE_InvalidateByRange((uint32_t)data->out_buf_addr, data->out_buf_size); in dma_mcux_pxp_irq_handler()
45 if (data->dma_callback) { in dma_mcux_pxp_irq_handler()
46 data->dma_callback(dev, data->user_data, 0, 0); in dma_mcux_pxp_irq_handler()
54 const struct dma_mcux_pxp_config *dev_config = dev->config; in dma_mcux_pxp_configure()
55 struct dma_mcux_pxp_data *dev_data = dev->data; in dma_mcux_pxp_configure()
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/Zephyr-latest/boards/witte/linum/
Dlinum.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h753bitx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &usart1;
22 zephyr,code-partition = &slot0_partition;
27 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "SDRAM1";
31 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
35 compatible = "gpio-leds";
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