| /hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/ |
| D | stm32h7xx_hal_flash.h | 107 #define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank …
108 #define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank …
109 #define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 …
110 #define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 …
112 #define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 …
114 #define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1…
115 #define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 …
116 #define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on …
117 #define HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on B…
118 #define HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1 …
[all …]
|
| D | stm32h7xx_ll_adc.h | 129 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
157 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
196 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
300 /* (feature of several watchdogs not available on all STM32 families)). */
304 /* selection on groups. */
366 …rty "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
380 …8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature…
381 …8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature…
384 …1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature…
385 …1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature…
[all …]
|
| /hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/ |
| D | stm32g4xx_ll_adc.h | 117 … compatibility with some ADC on other STM32 series
147 … compatibility with some ADC on other STM32 series
188 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
195 … of different ADC internal channels mapped on same channel
196 number on different ADC instances */
303 /* (feature of several watchdogs not available on all STM32 series)). */
307 /* selection on groups. */
365 Writing '0' has no effect on the bit value. */
377 …R_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4,
380 …R_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4,
[all …]
|
| D | stm32g4xx_ll_dac.h | 224 depending on the wave automatic generation selected. */
333 …eral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 series, p…
334 …eral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, p…
335 …eral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 series, p…
336 …eral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, p…
337 …eral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 series, p…
338 …eral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, p…
339 …eral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 series, p…
340 …eral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, p…
341 …eral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 series, p…
[all …]
|
| D | stm32g4xx_hal_adc.h | 63 … If oversampling is enabled on both regular and injected groups, this
83 * without conversion on going on group regular.
84 … parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
85 * on groups regular and injected.
88 * parameter (which fulfills the ADC state condition) on the fly).
97 … Note: In case of usage of channels on injected group, ADC frequency should be
101 … Note: In case of synchronous clock mode based on HCLK/1, the configuration must
117 data, based on following formula:
158 … Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
173 This parameter is dependent on ScanConvMode:
[all …]
|
| /hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/ |
| D | stm32f0xx_hal_dma_ex.h | 45 … 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */
46 … 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */
47 … 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */
48 … 0x30000000 /*!< Internal define for remapping on STM32F09x/30xC */
49 … 0x40000000 /*!< Internal define for remapping on STM32F09x/30xC */
51 … 0x50000000 /*!< Internal define for remapping on STM32F09x/30xC */
52 … 0x60000000 /*!< Internal define for remapping on STM32F09x/30xC */
53 … 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */
54 … 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */
55 … 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */
[all …]
|
| D | stm32f0xx_ll_adc.h | 52 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
86 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
140 /* (feature of several watchdogs not available on all STM32 families)). */
183 …rty "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
191 …x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature…
192 …x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature…
211 * @note These parameters have an impact on ADC scope: ADC instance.
220 * (setting possible with ADC enabled without conversion on going,
221 * ADC enabled with conversion on going, ...)
231 … @note On this STM32 series, this parameter has some clock ratio constraints:
[all …]
|
| /hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/ |
| D | stm32l4xx_ll_adc.h | 117 … compatibility with some ADC on other STM32 series
147 … compatibility with some ADC on other STM32 series
189 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
196 … of different ADC internal channels mapped on same channel
197 number on different ADC instances */
304 /* (feature of several watchdogs not available on all STM32 series)). */
308 /* selection on groups. */
366 Writing '0' has no effect on the bit value. */
378 …R_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32L4,
381 …R_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32L4,
[all …]
|
| /hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/ |
| D | stm32f3xx_ll_adc.h | 123 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
149 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
150 /* available on the selected device). */
154 /* available only on specific ADC instances. */
156 …r for differentiation of ADC group regular external trigger available only on ADC instance: ADC1, …
157 …r for differentiation of ADC group regular external trigger available only on ADC instance: ADC3, …
164 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
190 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
191 /* available on the selected device). */
195 /* available only on specific ADC instances. */
[all …]
|
| /hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/ |
| D | stm32u5xx_ll_adc.h | 172 … for compatibility with some ADC on other STM32
207 … compatibility with some ADC on other STM32 families
247 … aligned on register LSB (bit 0) */
269 … reduced range: on this STM32 series,
408 /* (feature of several watchdogs not available on all STM32 families)). */
412 /* selection on groups. */
482 … Writing '0' has no effect on the bit value. */
495 … TS_CAL1: On STM32U5, temperature sensor ADC raw
500 … TS_CAL2: On STM32U5, temperature sensor ADC raw
528 * (shift mask on register position bit 0).
[all …]
|
| /hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/ |
| D | stm32h5xx_ll_adc.h | 113 … compatibility with some ADC on other STM32 series
141 … compatibility with some ADC on other STM32 series
177 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
184 … of different ADC internal channels mapped on same channel
185 number on different ADC instances */
295 /* (feature of several watchdogs not available on all STM32 series)). */
299 /* selection on groups. */
357 Writing '0' has no effect on the bit value. */
369 …R_CAL1_ADDR ((uint16_t*) (0x08FFF814UL)) /* Address of parameter TS_CAL1: On STM32H5,
372 …R_CAL2_ADDR ((uint16_t*) (0x08FFF818UL)) /* Address of parameter TS_CAL2: On STM32H5,
[all …]
|
| /hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/ |
| D | stm32wb0x_hal_pwr_ex.h | 51 #define PWR_WAKEUP_PIN_RTC PWR_CR3_EIWL /*!< Enable wakeup on Internal event (R…
52 #define PWR_WAKEUP_PIN_LPUART PWR_CR3_EIWL2 /*!< Enable wakeup on Internal event 2 …
53 #define PWR_WAKEUP_BLEHOST PWR_CR3_EWBLEHCPU /*!< Enable wakeup on BLE Host CPU even…
54 #define PWR_WAKEUP_BLE PWR_CR3_EWBLE /*!< Enable wakeup on BLE event …
55 #define PWR_WAKEUP_PA11 PWR_CR3_EWU11 /*!< Enable wakeup on PA11 I/O event …
56 #define PWR_WAKEUP_PA10 PWR_CR3_EWU10 /*!< Enable wakeup on PA10 I/O event …
57 #define PWR_WAKEUP_PA9 PWR_CR3_EWU9 /*!< Enable wakeup on PA9 I/O event …
58 #define PWR_WAKEUP_PA8 PWR_CR3_EWU8 /*!< Enable wakeup on PA8 I/O event …
59 #define PWR_WAKEUP_PA3 (PWR_CR6_EWU15 << 16) /*!< Enable wakeup on PA3 I/O event …
60 #define PWR_WAKEUP_PA2 (PWR_CR6_EWU14 << 16) /*!< Enable wakeup on PA2 I/O event …
[all …]
|
| /hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/ |
| D | stm32wbxx_ll_adc.h | 56 /* No register ADC_SQRx on this ADC peripheral version */
129 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
157 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
200 …POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, A…
203 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
208 …DC instances, in case of different ADC internal channels mapped on same channel number on differen…
316 /* on one of the common sampling time available. */
342 /* (feature of several watchdogs not available on all STM32 families)). */
346 /* selection on groups. */
430 …rty "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
[all …]
|
| /hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/ |
| D | stm32l1xx_ll_adc.h | 136 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
164 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
201 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
214 …R0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices:…
301 /* (feature of several watchdogs not available on all STM32 families)). */
330 …_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature…
331 …_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature…
351 * (shift mask on register position bit 0).
395 … @note On this STM32 series, HSI RC oscillator is the only clock source for ADC.
397 … @note On this STM32 series, some clock ratio constraints between ADC clock and APB clock
[all …]
|
| /hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/ |
| D | stm32n6xx_ll_adc.h | 114 … for compatibility with some ADC on other STM32
143 … compatibility with some ADC on other STM32 series
174 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB */
299 /* (feature of several watchdogs not available on all STM32 series)). */
303 /* selection on groups. */
379 Writing '0' has no effect on the bit value. */
394 … On this STM32 series, it is required to load the OTP110 word before reading
507 * @note These parameters have an impact on ADC scope: ADC instance.
509 * of ADC group injected depends on STM32 series).
518 * (setting possible with ADC enabled without conversion on going,
[all …]
|
| /hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/ |
| D | stm32l5xx_ll_adc.h | 117 … compatibility with some ADC on other STM32 series
147 … compatibility with some ADC on other STM32 series
189 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
196 … of different ADC internal channels mapped on same channel
197 number on different ADC instances */
304 /* (feature of several watchdogs not available on all STM32 series)). */
308 /* selection on groups. */
366 Writing '0' has no effect on the bit value. */
378 …R_CAL1_ADDR ((uint16_t*) (0x0BFA05A8UL)) /* Address of parameter TS_CAL1: On STM32L5,
381 …R_CAL2_ADDR ((uint16_t*) (0x0BFA05CAUL)) /* Address of parameter TS_CAL2: On STM32L5,
[all …]
|
| /hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/ |
| D | stm32l0xx_ll_adc.h | 52 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
86 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
142 /* (feature of several watchdogs not available on all STM32 families)). */
187 …rty "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
195 /* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */
197 …x1FF8007AU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L0, temperature…
199 …x1FF8007EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L0, temperature…
252 * @note These parameters have an impact on ADC scope: ADC instance.
261 * (setting possible with ADC enabled without conversion on going,
262 * ADC enabled with conversion on going, ...)
[all …]
|
| /hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/ |
| D | stm32f1xx_ll_adc.h | 116 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
121 …DC instances, in case of different ADC internal channels mapped on same channel number on differen…
178 /* (feature of several watchdogs not available on all STM32 families)). */
211 * (shift mask on register position bit 0).
260 * @note These parameters have an impact on ADC scope: ADC instance.
262 * of ADC group injected depends on STM32 families).
271 * (setting possible with ADC enabled without conversion on going,
272 * ADC enabled with conversion on going, ...)
294 * @note These parameters have an impact on ADC scope: ADC group regular.
304 * (setting possible with ADC enabled without conversion on going,
[all …]
|
| /hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/ |
| D | stm32c0xx_ll_adc.h | 71 … compatibility with some ADC on other STM32 series
104 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
111 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
178 /* on one of the common sampling time available. */
188 /* (feature of several watchdogs not available on all STM32 series)). */
192 /* selection on groups. */
266 on the bit value. */
278 /* Note: On all devices of series STM32C0, calibration parameter TS_CAL2 is not available.
286 … parameter TS_CAL1: On STM32C0, temperature sensor ADC raw data acquired at
349 * @note These parameters have an impact on ADC scope: ADC instance.
[all …]
|
| /hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/ |
| D | stm32mp1xx_ll_adc.h | 131 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
159 …r edge set to rising edge (default setting for compatibility with some ADC on other STM32 families…
199 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
304 /* (feature of several watchdogs not available on all STM32 families)). */
308 /* selection on groups. */
358 …rty "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
366 …5C00525CUL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32MP1, temperatur…
367 …5C00525EUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32MP1, temperatur…
420 … @note On this STM32 series, if ADC group injected is used, some
447 * @note These parameters have an impact on ADC scope: ADC instance.
[all …]
|
| /hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/ |
| D | stm32g0xx_ll_adc.h | 72 … compatibility with some ADC on other STM32 series
106 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
113 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
171 /* on one of the common sampling time available. */
181 /* (feature of several watchdogs not available on all STM32 series)). */
185 /* selection on groups. */
256 Writing '0' has no effect on the bit value. */
268 …R_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G0,
271 …R_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G0,
337 * @note These parameters have an impact on ADC scope: ADC instance.
[all …]
|
| /hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/ |
| D | stm32wbaxx_ll_adc.h | 71 … compatibility with some ADC on other STM32 series
104 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
111 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
168 /* on one of the common sampling time available. */
178 /* (feature of several watchdogs not available on all STM32 series)). */
182 /* selection on groups. */
249 Writing '0' has no effect on the bit value. */
261 …L1_ADDR ((uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series,
264 …L2_ADDR ((uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series,
290 * (shift mask on register position bit 0).
[all …]
|
| /hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/ |
| D | stm32h7rsxx_ll_adc.h | 117 … compatibility with some ADC on other STM32 series
147 … compatibility with some ADC on other STM32 series
188 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
195 … of different ADC internal channels mapped on same channel
196 number on different ADC instances */
303 /* (feature of several watchdogs not available on all STM32 series)). */
307 /* selection on groups. */
365 Writing '0' has no effect on the bit value. */
377 …CAL1_ADDR ((uint16_t*) (0x1FF1E814UL)) /* Address of parameter TS_CAL1: On STM32H7RS,
380 …CAL2_ADDR ((uint16_t*) (0x1FF1E818UL)) /* Address of parameter TS_CAL2: On STM32H7RS,
[all …]
|
| /hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/ |
| D | stm32f3xx_hal_adc_ex.c | 67 /* Timeout to wait for current conversion on going to be completed. */
102 /* been in power-on state for at least two ADC clock cycles. */
201 * depending on possible clock sources: AHB clock or PLL clock.
204 * @note Possibility to update parameters on the fly:
208 * structure on the fly, without modifying MSP configuration. If ADC
222 * case of update of a parameter of ADC_InitTypeDef on the fly,
270 /* Refer to header of this file for more details on clock enabling */ in HAL_ADC_Init()
368 /* correctly completed and if there is no conversion on going on regular */ in HAL_ADC_Init()
370 /* called to update a parameter on the fly). */ in HAL_ADC_Init()
383 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ in HAL_ADC_Init()
[all …]
|
| /hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/ |
| D | stm32wlxx_ll_adc.h | 72 … compatibility with some ADC on other STM32 families
106 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
113 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
170 /* on one of the common sampling time available. */
180 /* (feature of several watchdogs not available on all STM32 families)). */
184 /* selection on groups. */
254 …HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit …
265 …R_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32WL,
268 …R_CAL2_ADDR ((uint16_t*) (0x1FFF75C8UL)) /* Address of parameter TS_CAL2: On STM32WL,
331 * @note These parameters have an impact on ADC scope: ADC instance.
[all …]
|
