1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_dma_ex.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F0xx_HAL_DMA_EX_H 21 #define __STM32F0xx_HAL_DMA_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f0xx_hal_def.h" 29 30 /** @addtogroup STM32F0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup DMAEx DMAEx 35 * @brief DMA HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /* Exported constants --------------------------------------------------------*/ 41 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 42 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants 43 * @{ 44 */ 45 #define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */ 46 #define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */ 47 #define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */ 48 #define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remapping on STM32F09x/30xC */ 49 #define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remapping on STM32F09x/30xC */ 50 #if !defined(STM32F030xC) 51 #define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remapping on STM32F09x/30xC */ 52 #define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remapping on STM32F09x/30xC */ 53 #define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */ 54 #define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */ 55 #define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */ 56 #define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remapping on STM32F09x/30xC */ 57 #define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remapping on STM32F09x/30xC */ 58 #endif /* !defined(STM32F030xC) */ 59 60 /****************** DMA1 remap bit field definition********************/ 61 /* DMA1 - Channel 1 */ 62 #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ 63 #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ 64 #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ 65 #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ 66 #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ 67 #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ 68 #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ 69 #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ 70 #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ 71 #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ 72 #if !defined(STM32F030xC) 73 #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ 74 #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ 75 #endif /* !defined(STM32F030xC) */ 76 77 /* DMA1 - Channel 2 */ 78 #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ 79 #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ 80 #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ 81 #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ 82 #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ 83 #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ 84 #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ 85 #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ 86 #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ 87 #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ 88 #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ 89 #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ 90 #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ 91 #if !defined(STM32F030xC) 92 #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ 93 #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ 94 #endif /* !defined(STM32F030xC) */ 95 96 /* DMA1 - Channel 3 */ 97 #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ 98 #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ 99 #if !defined(STM32F030xC) 100 #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ 101 #endif /* !defined(STM32F030xC) */ 102 #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ 103 #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ 104 #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ 105 #if !defined(STM32F030xC) 106 #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ 107 #endif /* !defined(STM32F030xC) */ 108 #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ 109 #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ 110 #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ 111 #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ 112 #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ 113 #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ 114 #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ 115 #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ 116 #if !defined(STM32F030xC) 117 #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ 118 #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ 119 #endif /* !defined(STM32F030xC) */ 120 121 /* DMA1 - Channel 4 */ 122 #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ 123 #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ 124 #if !defined(STM32F030xC) 125 #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ 126 #endif /* !defined(STM32F030xC) */ 127 #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ 128 #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ 129 #if !defined(STM32F030xC) 130 #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ 131 #endif /* !defined(STM32F030xC) */ 132 #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ 133 #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ 134 #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ 135 #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ 136 #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ 137 #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ 138 #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ 139 #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ 140 #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ 141 #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ 142 #if !defined(STM32F030xC) 143 #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ 144 #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ 145 #endif /* !defined(STM32F030xC) */ 146 147 /* DMA1 - Channel 5 */ 148 #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ 149 #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ 150 #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ 151 #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ 152 #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ 153 #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ 154 #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ 155 #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ 156 #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ 157 #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ 158 #if !defined(STM32F030xC) 159 #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ 160 #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ 161 #endif /* !defined(STM32F030xC) */ 162 163 #if !defined(STM32F030xC) 164 /* DMA1 - Channel 6 */ 165 #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ 166 #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ 167 #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ 168 #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ 169 #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ 170 #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ 171 #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ 172 #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ 173 #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ 174 #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ 175 #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ 176 #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ 177 #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ 178 #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ 179 #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ 180 #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ 181 #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ 182 #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ 183 /* DMA1 - Channel 7 */ 184 #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ 185 #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ 186 #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ 187 #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ 188 #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ 189 #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ 190 #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ 191 #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ 192 #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ 193 #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ 194 #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ 195 #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ 196 #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ 197 #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ 198 #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ 199 200 /****************** DMA2 remap bit field definition********************/ 201 /* DMA2 - Channel 1 */ 202 #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ 203 #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ 204 #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ 205 #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ 206 #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ 207 #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ 208 #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ 209 #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ 210 #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ 211 #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ 212 /* DMA2 - Channel 2 */ 213 #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ 214 #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ 215 #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ 216 #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ 217 #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ 218 #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ 219 #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ 220 #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ 221 #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ 222 #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ 223 /* DMA2 - Channel 3 */ 224 #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ 225 #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ 226 #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ 227 #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ 228 #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ 229 #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ 230 #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ 231 #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ 232 #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ 233 #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ 234 #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ 235 #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ 236 /* DMA2 - Channel 4 */ 237 #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ 238 #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ 239 #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ 240 #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ 241 #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ 242 #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ 243 #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ 244 #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ 245 #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ 246 #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ 247 #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ 248 #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ 249 /* DMA2 - Channel 5 */ 250 #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ 251 #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ 252 #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ 253 #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ 254 #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ 255 #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ 256 #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ 257 #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ 258 #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ 259 #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ 260 #endif /* !defined(STM32F030xC) */ 261 262 #if defined(STM32F091xC) || defined(STM32F098xx) 263 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ 264 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ 265 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ 266 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ 267 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ 268 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ 269 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ 270 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ 271 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ 272 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ 273 ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ 274 ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ 275 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ 276 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ 277 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ 278 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ 279 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ 280 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ 281 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ 282 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ 283 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ 284 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ 285 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ 286 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ 287 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ 288 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ 289 ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ 290 ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ 291 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ 292 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ 293 ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ 294 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ 295 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ 296 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ 297 ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ 298 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ 299 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ 300 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ 301 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ 302 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ 303 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ 304 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ 305 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ 306 ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ 307 ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ 308 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ 309 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ 310 ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ 311 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ 312 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ 313 ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ 314 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ 315 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ 316 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ 317 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ 318 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ 319 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ 320 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ 321 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ 322 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ 323 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ 324 ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ 325 ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ 326 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ 327 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ 328 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ 329 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ 330 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ 331 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ 332 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ 333 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ 334 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ 335 ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ 336 ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ 337 ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ 338 ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ 339 ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ 340 ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ 341 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ 342 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ 343 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ 344 ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ 345 ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ 346 ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ 347 ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ 348 ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ 349 ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ 350 ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ 351 ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ 352 ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ 353 ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ 354 ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ 355 ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ 356 ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ 357 ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ 358 ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ 359 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ 360 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ 361 ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ 362 ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ 363 ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ 364 ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ 365 ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ 366 ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ 367 ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ 368 ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ 369 ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ 370 ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) 371 372 #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ 373 ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ 374 ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ 375 ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ 376 ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ 377 ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ 378 ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ 379 ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ 380 ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ 381 ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ 382 ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ 383 ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ 384 ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ 385 ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ 386 ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ 387 ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ 388 ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ 389 ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ 390 ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ 391 ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ 392 ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ 393 ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ 394 ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ 395 ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ 396 ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ 397 ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ 398 ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ 399 ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ 400 ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ 401 ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ 402 ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ 403 ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ 404 ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ 405 ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ 406 ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ 407 ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ 408 ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ 409 ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ 410 ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ 411 ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ 412 ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ 413 ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ 414 ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ 415 ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ 416 ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ 417 ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ 418 ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ 419 ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ 420 ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ 421 ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ 422 ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ 423 ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ 424 ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ 425 ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) 426 #endif /* STM32F091xC || STM32F098xx */ 427 428 #if defined(STM32F030xC) 429 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ 430 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ 431 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ 432 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ 433 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ 434 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ 435 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ 436 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ 437 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ 438 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ 439 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ 440 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ 441 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ 442 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ 443 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ 444 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ 445 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ 446 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ 447 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ 448 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ 449 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ 450 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ 451 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ 452 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ 453 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ 454 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ 455 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ 456 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ 457 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ 458 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ 459 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ 460 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ 461 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ 462 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ 463 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ 464 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ 465 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ 466 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ 467 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ 468 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ 469 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ 470 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ 471 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ 472 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ 473 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ 474 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ 475 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ 476 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ 477 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ 478 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ 479 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ 480 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ 481 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ 482 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ 483 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ 484 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ 485 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ 486 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ 487 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ 488 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ 489 ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) 490 #endif /* STM32F030xC */ 491 492 /** 493 * @} 494 */ 495 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 496 497 /* Exported macros -----------------------------------------------------------*/ 498 499 /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros 500 * @{ 501 */ 502 /* Interrupt & Flag management */ 503 504 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) 505 /** 506 * @brief Returns the current DMA Channel transfer complete flag. 507 * @param __HANDLE__ DMA handle 508 * @retval The specified transfer complete flag index. 509 */ 510 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 511 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 517 DMA_FLAG_TC7) 518 519 /** 520 * @brief Returns the current DMA Channel half transfer complete flag. 521 * @param __HANDLE__ DMA handle 522 * @retval The specified half transfer complete flag index. 523 */ 524 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 525 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 531 DMA_FLAG_HT7) 532 533 /** 534 * @brief Returns the current DMA Channel transfer error flag. 535 * @param __HANDLE__ DMA handle 536 * @retval The specified transfer error flag index. 537 */ 538 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 539 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 545 DMA_FLAG_TE7) 546 547 /** 548 * @brief Return the current DMA Channel Global interrupt flag. 549 * @param __HANDLE__ DMA handle 550 * @retval The specified transfer error flag index. 551 */ 552 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 553 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ 554 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ 555 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ 556 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ 557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ 559 DMA_FLAG_GL7) 560 561 /** 562 * @brief Get the DMA Channel pending flags. 563 * @param __HANDLE__ DMA handle 564 * @param __FLAG__ Get the specified flag. 565 * This parameter can be any combination of the following values: 566 * @arg DMA_FLAG_TCx: Transfer complete flag 567 * @arg DMA_FLAG_HTx: Half transfer complete flag 568 * @arg DMA_FLAG_TEx: Transfer error flag 569 * Where x can be 1_7 to select the DMA Channel flag. 570 * @retval The state of FLAG (SET or RESET). 571 */ 572 573 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 574 575 /** 576 * @brief Clears the DMA Channel pending flags. 577 * @param __HANDLE__ DMA handle 578 * @param __FLAG__ specifies the flag to clear. 579 * This parameter can be any combination of the following values: 580 * @arg DMA_FLAG_TCx: Transfer complete flag 581 * @arg DMA_FLAG_HTx: Half transfer complete flag 582 * @arg DMA_FLAG_TEx: Transfer error flag 583 * Where x can be 1_7 to select the DMA Channel flag. 584 * @retval None 585 */ 586 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 587 588 #elif defined(STM32F091xC) || defined(STM32F098xx) 589 /** 590 * @brief Returns the current DMA Channel transfer complete flag. 591 * @param __HANDLE__ DMA handle 592 * @retval The specified transfer complete flag index. 593 */ 594 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 595 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 601 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ 602 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 603 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 604 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 605 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 606 DMA_FLAG_TC5) 607 608 /** 609 * @brief Returns the current DMA Channel half transfer complete flag. 610 * @param __HANDLE__ DMA handle 611 * @retval The specified half transfer complete flag index. 612 */ 613 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 614 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 615 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 616 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 617 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 618 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ 621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 622 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 623 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 624 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 625 DMA_FLAG_HT5) 626 627 /** 628 * @brief Returns the current DMA Channel transfer error flag. 629 * @param __HANDLE__ DMA handle 630 * @retval The specified transfer error flag index. 631 */ 632 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 633 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 635 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 636 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 637 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ 640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 641 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 642 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 643 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 644 DMA_FLAG_TE5) 645 646 /** 647 * @brief Return the current DMA Channel Global interrupt flag. 648 * @param __HANDLE__ DMA handle 649 * @retval The specified transfer error flag index. 650 */ 651 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 652 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ 653 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ 658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ 659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ 660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ 661 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ 662 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ 663 DMA_FLAG_GL5) 664 665 /** 666 * @brief Get the DMA Channel pending flags. 667 * @param __HANDLE__ DMA handle 668 * @param __FLAG__ Get the specified flag. 669 * This parameter can be any combination of the following values: 670 * @arg DMA_FLAG_TCx: Transfer complete flag 671 * @arg DMA_FLAG_HTx: Half transfer complete flag 672 * @arg DMA_FLAG_TEx: Transfer error flag 673 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 674 * @retval The state of FLAG (SET or RESET). 675 */ 676 677 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 678 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ 679 (DMA1->ISR & (__FLAG__))) 680 681 /** 682 * @brief Clears the DMA Channel pending flags. 683 * @param __HANDLE__ DMA handle 684 * @param __FLAG__ specifies the flag to clear. 685 * This parameter can be any combination of the following values: 686 * @arg DMA_FLAG_TCx: Transfer complete flag 687 * @arg DMA_FLAG_HTx: Half transfer complete flag 688 * @arg DMA_FLAG_TEx: Transfer error flag 689 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 690 * @retval None 691 */ 692 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 693 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ 694 (DMA1->IFCR = (__FLAG__))) 695 696 #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ 697 /** 698 * @brief Returns the current DMA Channel transfer complete flag. 699 * @param __HANDLE__ DMA handle 700 * @retval The specified transfer complete flag index. 701 */ 702 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 703 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 704 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 705 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 706 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 707 DMA_FLAG_TC5) 708 709 /** 710 * @brief Returns the current DMA Channel half transfer complete flag. 711 * @param __HANDLE__ DMA handle 712 * @retval The specified half transfer complete flag index. 713 */ 714 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 715 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 716 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 717 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 718 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 719 DMA_FLAG_HT5) 720 721 /** 722 * @brief Returns the current DMA Channel transfer error flag. 723 * @param __HANDLE__ DMA handle 724 * @retval The specified transfer error flag index. 725 */ 726 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 727 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 728 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 729 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 730 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 731 DMA_FLAG_TE5) 732 733 /** 734 * @brief Return the current DMA Channel Global interrupt flag. 735 * @param __HANDLE__ DMA handle 736 * @retval The specified transfer error flag index. 737 */ 738 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 739 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ 740 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ 741 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ 742 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ 743 DMA_FLAG_GL5) 744 745 /** 746 * @brief Get the DMA Channel pending flags. 747 * @param __HANDLE__ DMA handle 748 * @param __FLAG__ Get the specified flag. 749 * This parameter can be any combination of the following values: 750 * @arg DMA_FLAG_TCx: Transfer complete flag 751 * @arg DMA_FLAG_HTx: Half transfer complete flag 752 * @arg DMA_FLAG_TEx: Transfer error flag 753 * Where x can be 1_5 to select the DMA Channel flag. 754 * @retval The state of FLAG (SET or RESET). 755 */ 756 757 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 758 759 /** 760 * @brief Clears the DMA Channel pending flags. 761 * @param __HANDLE__ DMA handle 762 * @param __FLAG__ specifies the flag to clear. 763 * This parameter can be any combination of the following values: 764 * @arg DMA_FLAG_TCx: Transfer complete flag 765 * @arg DMA_FLAG_HTx: Half transfer complete flag 766 * @arg DMA_FLAG_TEx: Transfer error flag 767 * Where x can be 1_5 to select the DMA Channel flag. 768 * @retval None 769 */ 770 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 771 772 #endif 773 774 775 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 776 #define __HAL_DMA1_REMAP(__REQUEST__) \ 777 do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ 778 DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ 779 DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ 780 }while(0) 781 782 #if defined(STM32F091xC) || defined(STM32F098xx) 783 #define __HAL_DMA2_REMAP(__REQUEST__) \ 784 do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ 785 DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ 786 DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ 787 }while(0) 788 #endif /* STM32F091xC || STM32F098xx */ 789 790 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 791 792 /** 793 * @} 794 */ 795 796 /** 797 * @} 798 */ 799 800 /** 801 * @} 802 */ 803 804 #ifdef __cplusplus 805 } 806 #endif 807 808 #endif /* __STM32F0xx_HAL_DMA_EX_H */ 809 810
