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/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_shrtimer.h31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
871 …0_TRG0MTC0 BIT(0) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare…
872 …0_TRG0MTC1 BIT(1) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare…
873 …0_TRG0MTC2 BIT(2) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare…
874 …0_TRG0MTC3 BIT(3) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER compare…
875 …0_TRG0MTPER BIT(4) /*!< SHRTIMER_ADCTRIG0 on Master_TIMER period …
876 …GS0_TRG0EXEV0 BIT(5) /*!< SHRTIMER_ADCTRIG0 on external event 0 */
877 …GS0_TRG0EXEV1 BIT(6) /*!< SHRTIMER_ADCTRIG0 on external event 1 */
878 …GS0_TRG0EXEV2 BIT(7) /*!< SHRTIMER_ADCTRIG0 on external event 2 */
879 …GS0_TRG0EXEV3 BIT(8) /*!< SHRTIMER_ADCTRIG0 on external event 3 */
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/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_mfcom.h29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
241 …_TMOUT(2) /*!< logic one when enabled and on timer reset */
242 …TMOUT(3) /*!< logic zero when enabled and on timer reset */
246 …FG_TMDEC(0) /*!< decrement counter on MFCOM clock, shift c…
247 …FG_TMDEC(1) /*!< decrement counter on trigger input (both …
248 …FG_TMDEC(2) /*!< decrement counter on pin input (both edge…
249 …FG_TMDEC(3) /*!< decrement counter on trigger input (both …
254 … TMCFG_TMRST(2) /*!< timer reset on timer pin equal to t…
255 … TMCFG_TMRST(3) /*!< timer reset on timer trigger equal …
256 … TMCFG_TMRST(4) /*!< timer reset on timer pin rising edg…
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Dgd32a50x_fwdgt.h29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
92 …AT_PUD /*!< a write operation to FWDGT_PSC register is on going */
93 …AT_RUD /*!< a write operation to FWDGT_RLD register is on going */
94 …AT_WUD /*!< a write operation to FWDGT_WND register is on going */
/hal_gigadevice-latest/pinconfigs/
DREADME.md18 *AFIO model*. Alternate function tables (AF0..15) will only be available on
64 available. If not defined, it is assumed that signal is available on all
67 available. If not defined, it is assumed that signal is available on all
91 # Configuration for 'ADC01_IN0': available on all pincodes/memories, can
95 # Configuration for 'I2S2_CK': available on all pincodes, all memories except
102 # Configuration for pin 'PA0'. Supported on V, R, C, T pincodes, valid
124 available. If not defined, it is assumed that signal is available on all
128 available. If not available, it is assumed that signal is available on all
143 # Configuration for 'EXMC_NOE': available on all memories except 6, 4.
148 # Configuration for pin 'PA0'. Available on pin codes I, Z, V and has
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/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_slcd.c29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
205 \arg SLCD_BLINKMODE_SEG0_COM0: blink enabled on SEG[0], COM[0]
206 \arg SLCD_BLINKMODE_SEG0_ALLCOM: blink enabled on SEG[0], all COM
207 \arg SLCD_BLINKMODE_ALLSEG_ALLCOM: blink enabled on all SEG and all COM
281 \brief configure SLCD pulse on duration
282 \param[in] pulseonduration: specifies the slcd pulse on duration
284 \arg SLCD_PULSEON_DURATION_0: pulse on duration = 0
285 \arg SLCD_PULSEON_DURATION_1: pulse on duration = 1*1/fPRE
286 \arg SLCD_PULSEON_DURATION_2: pulse on duration = 2*1/fPRE
287 \arg SLCD_PULSEON_DURATION_3: pulse on duration = 3*1/fPRE
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Dgd32l23x_crc.c29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
139 \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
140 \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
141 \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
Dgd32l23x_fwdgt.c29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
238 \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
239 \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
240 \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_slcd.h29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
70 #define SLCD_CFG_PULSE BITS(4,6) /*!< pulse on duration …
79 #define SLCD_STAT_ONF BIT(0) /*!< controller on flag…
111 /* SLCD pulse on duration definitions */
113 #define SLCD_PULSEON_DURATION_0 CFG_PULSE(0) /*!< pulse on duration …
114 #define SLCD_PULSEON_DURATION_1 CFG_PULSE(1) /*!< pulse on duration …
115 #define SLCD_PULSEON_DURATION_2 CFG_PULSE(2) /*!< pulse on duration …
116 #define SLCD_PULSEON_DURATION_3 CFG_PULSE(3) /*!< pulse on duration …
117 #define SLCD_PULSEON_DURATION_4 CFG_PULSE(4) /*!< pulse on duration …
118 #define SLCD_PULSEON_DURATION_5 CFG_PULSE(5) /*!< pulse on duration …
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Dgd32l23x_fwdgt.h29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
92 …AT_PUD /*!< a write operation to FWDGT_PSC register is on going */
93 …AT_RUD /*!< a write operation to FWDGT_RLD register is on going */
94 …AT_WUD /*!< a write operation to FWDGT_WND register is on going */
Dgd32l23x_adc.h29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
81 … /*!< when in scan mode, analog watchdog is effective on a single channel */
83 … BIT(11) /*!< discontinuous mode on regular channels */
84 … BIT(12) /*!< discontinuous mode on inserted channels */
86 … BIT(22) /*!< analog watchdog enable on inserted channels */
87 … BIT(23) /*!< analog watchdog enable on regular channels */
91 …DC_CTL1_ADCON BIT(0) /*!< ADC converter on */
101 #define ADC_CTL1_SWICST BIT(21) /*!< start on i…
102 #define ADC_CTL1_SWRCST BIT(22) /*!< start on r…
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_gpio.c31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
344 \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(not support on GD32EPRT devices)
345 \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(not support on GD32EPRT devices)
353 \arg GPIO_CAN1_REMAP: CAN1 remapping(not support on GD32EPRT devices)
360 \arg GPIO_TIMER8_REMAP: TIMER8 remapping(not support on GD32EPRT devices)
361 \arg GPIO_TIMER9_REMAP: TIMER9 remapping(not support on GD32EPRT devices)
362 \arg GPIO_TIMER10_REMAP: TIMER10 remapping(not support on GD32EPRT devices)
363 \arg GPIO_TIMER12_REMAP: TIMER12 remapping(not support on GD32EPRT devices)
364 \arg GPIO_TIMER13_REMAP: TIMER13 remapping(not support on GD32EPRT devices)
416 … \param[in] afio_function: select the port AFIO function(SHRTIMER not support on GD32EPRT devices)
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Dgd32e50x_crc.c31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
93 \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
94 \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
95 \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_cec.c31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
101 \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error
102 \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error
105 \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error
106 \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error
252 \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error
253 \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error
256 \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error
257 \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error
Dgd32f3x0_fwdgt.c31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
169 \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
170 \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
171 \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
Dgd32f3x0_crc.c31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
141 \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
142 \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
143 \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_syscfg.c29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
114 \arg SYSCFG_PA9_PA12_REMAP: PA9/PA12 pins are mapping on PA10/PA11 pins
115 \arg SYSCFG_BOOT0_REMAP_PF0: PF0 pin is mapping on the BOOT0 pin
128 \arg SYSCFG_PA9_PA12_REMAP: PA9/PA12 pins are mapping on PA10/PA11 pins
129 \arg SYSCFG_BOOT0_REMAP_PF0: PF0 pin is mapping on the BOOT0 pin
434 \brief get the address where SRAM ECC error occur on
437 \retval uint16_t: the address where SRAM ECC error occur on
Dgd32a50x_fwdgt.c29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
231 \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
232 \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
233 \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
Dgd32a50x_crc.c29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
139 \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
140 \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
141 \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_adc.h31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
82 … /*!< when in scan mode, analog watchdog is effective on a single channel */
84 … BIT(11) /*!< discontinuous mode on regular channels */
85 … BIT(12) /*!< discontinuous mode on inserted channels */
87 … BIT(22) /*!< analog watchdog enable on inserted channels */
88 … BIT(23) /*!< analog watchdog enable on regular channels */
92 #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on …
102 #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted…
103 #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular …
Dgd32f3x0_fwdgt.h31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
103 …GT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
104 …GT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
105 …GT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_i2c.c30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
312 \brief generate a START condition on I2C bus
323 \brief generate a STOP condition on I2C bus
462 \brief I2C PEC calculation on or off
466 \arg I2C_PEC_ENABLE: PEC calculation on
473 /* on/off PEC calculation */ in i2c_pec_enable()
568 … I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
665 …G_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt fl…
707 …G_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt fl…
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_adc.h30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
82 … /*!< when in scan mode, analog watchdog is effective on a single channel */
84 #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on…
85 #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on…
88 … BIT(22) /*!< analog watchdog enable on inserted channels */
89 … BIT(23) /*!< analog watchdog enable on regular channels */
92 #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
102 #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted cha…
103 #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular chan…
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_i2c.c32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
321 \brief generate a START condition on I2C bus
332 \brief generate a STOP condition on I2C bus
471 \brief I2C PEC calculation on or off
475 \arg I2C_PEC_ENABLE: PEC calculation on
482 /* on/off PEC calculation */ in i2c_pec_enable()
577 … I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
674 …G_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt fl…
716 …G_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt fl…
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_adc.h32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
84 … /*!< when in scan mode, analog watchdog is effective on a single channel */
86 #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on…
87 #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on…
90 … BIT(22) /*!< analog watchdog enable on inserted channels */
91 … BIT(23) /*!< analog watchdog enable on regular channels */
94 #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
104 #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted cha…
105 #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular chan…
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_pmu.h32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
73 #define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */
122 /* PMU backup SRAM LDO on or off */
125 #define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on…
193 /* backup SRAM LDO on */

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