1 /*! 2 \file gd32fxxx_fwdgt.h 3 \brief definitions for the FWDGT 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 36 #ifndef GD32A50X_FWDGT_H 37 #define GD32A50X_FWDGT_H 38 39 #include "gd32a50x.h" 40 41 /* FWDGT definitions */ 42 #define FWDGT FWDGT_BASE /*!< FWDGT base address */ 43 44 /* registers definitions */ 45 #define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ 46 #define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ 47 #define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ 48 #define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ 49 #define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */ 50 51 /* bits definitions */ 52 /* FWDGT_CTL */ 53 #define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ 54 55 /* FWDGT_PSC */ 56 #define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ 57 58 /* FWDGT_RLD */ 59 #define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ 60 61 /* FWDGT_STAT */ 62 #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ 63 #define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ 64 #define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ 65 66 /* FWDGT_WND */ 67 #define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ 68 69 /* constants definitions */ 70 /* FWDGT_PSC register value */ 71 #define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) 72 #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ 73 #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ 74 #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ 75 #define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ 76 #define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ 77 #define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ 78 #define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ 79 80 /* control value */ 81 #define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ 82 #define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ 83 #define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ 84 #define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ 85 86 /* FWDGT timeout value */ 87 #define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ 88 #define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ 89 #define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ 90 91 /* FWDGT flag definitions */ 92 #define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ 93 #define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ 94 #define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ 95 96 /* write value to FWDGT_RLD_RLD bit field */ 97 #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */ 98 /* write value to FWDGT_WND_WND bit field */ 99 #define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */ 100 101 /* function declarations */ 102 /* enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */ 103 void fwdgt_write_enable(void); 104 /* disable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */ 105 void fwdgt_write_disable(void); 106 /* start the FWDGT counter */ 107 void fwdgt_enable(void); 108 109 /* configure the FWDGT counter prescaler value */ 110 ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); 111 /* configure the FWDGT counter reload value */ 112 ErrStatus fwdgt_reload_value_config(uint16_t reload_value); 113 /* configure the FWDGT counter window value */ 114 ErrStatus fwdgt_window_value_config(uint16_t window_value); 115 /* reload the counter of FWDGT */ 116 void fwdgt_counter_reload(void); 117 /* configure counter reload value, and prescaler divider value */ 118 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); 119 120 /* get flag state of FWDGT */ 121 FlagStatus fwdgt_flag_get(uint16_t flag); 122 123 #endif /* GD32A50X_FWDGT_H */ 124
