Home
last modified time | relevance | path

Searched full:mspi (Results 1 – 25 of 68) sorted by relevance

123

/hal_espressif-latest/components/esp_hw_support/include/esp_private/
Dmspi_timing_tuning.h9 * This file is for MSPI timinig tuning private APIs
22 * @brief Make MSPI work under 20Mhz, remove the timing tuning required delays.
28 …* @brief Make MSPI work under the frequency as users set, may add certain delays to MSPI RX direct…
34 * @brief Switch MSPI into low speed mode / high speed mode.
35 …* @note This API is cache safe, it will freeze both D$ and I$ and restore them after MSPI is switc…
36 …* @note For some of the MSPI high frequency settings (e.g. 80M DDR mode Flash or PSRAM), timing tu…
37 …* Certain delays will be added to the MSPI RX direction. When CPU clock switches from PLL to…
38 * this API first to enter MSPI low speed mode to remove the delays, and vice versa.
43 * @brief Tune MSPI flash timing to make it work under high frequency
48 * @brief Tune MSPI psram timing to make it work under high frequency
[all …]
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmspi_timing_tuning_ll.h50 * Set all MSPI pin drive strength
73 * Set all MSPI Flash clock pin drive strength
88 * Set all MSPI PSRAM clock pin drive strength
137 * Set MSPI core clock divider
149 * Set MSPI Flash clock
166 * Set MSPI PSRAM clock
183 * Set MSPI Flash din mode
198 * Set MSPI Flash din num
213 * Get MSPI Flash mode
248 * Set MSPI Octal Flash extra dummy
[all …]
/hal_espressif-latest/components/spi_flash/include/esp_private/
Dspi_flash_os.h8 * System level MSPI APIs (private)
27 // Type of MSPI IO
45 ESP_MSPI_IO_MAX, /* Maximum IO MSPI occupied */
49 * @brief To initislize the MSPI pins
54 * @brief Get the number of the GPIO corresponding to the given MSPI io
56 * @param[in] io MSPI io
58 * @return MSPI IO number
81 * @brief Get the knowledge if the MSPI timing is tuned or not
86 * @brief Set Flash chip specifically required MSPI register settings here
128 …* @note Don't forget to subtract one when assign to the register of mspi e.g. if the value you get…
[all …]
/hal_espressif-latest/components/esp_hw_support/
Dmspi_timing_config.h56 * @brief Set MSPI core clock
64 * @brief Set MSPI Flash module clock
72 * @brief Set MSPI Flash Din Mode and Din Num
81 * @brief Set MSPI Flash extra dummy
98 * @brief Set MSPI PSRAM module clock
106 * @brief Set MSPI PSRAM Din Mode and Din Num
115 * @brief Set MSPI PSRAM extra dummy
Dsleep_gpio.c127 * - task stack is located in external ram(mspi ram), since we will isolate mspi io in esp_sleep_isolate_digital_gpio()
D.build-test-rules.yml20 components/esp_hw_support/test_apps/mspi:
Dmspi_timing_tuning.c29 const static char *TAG = "MSPI Timing";
110 …* We use different SPI1 timing tuning config to read data to see if current MSPI sampling is succe…
272 //This `max_freq` is the max pll frequency that per MSPI timing tuning config can work in select_best_tuning_config_dtr()
575 //enter MSPI low speed mode, extra delays should be removed in mspi_timing_change_speed_mode_cache_safe()
578 //enter MSPI high speed mode, extra delays should be considered in mspi_timing_change_speed_mode_cache_safe()
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dspi_mem_struct.h40 …1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_D…
41 … /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[…
42 … : 1; /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7…
43 … : 1; /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[…
75 … 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real …
76 …nt32_t reg_aw_size0_1_support_en : 1; /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, M…
98 …ransfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
109 … 1; /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
204 …f_en : 1; /*Set this bit to close AXI read/write transfer to MSPI, which means that o…
242 …In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of…
[all …]
Dxts_aes_reg.h66 /*description: Set this bit to release encrypted result to mspi. This action should only be ass
88 sible to mspi, 3: the encrypted result is visible to mspi..*/
103 /*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
Dspi_mem_reg.h281 /*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
282 is output by the MSPI controller in the second half part of dummy phase. It is u
289 /*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
290 s output by the MSPI controller in the first half part of dummy phase. It is use
297 /*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
298 vel of SPI_IO[7:0] is output by the MSPI controller..*/
304 /*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
305 vel of SPI_DQS is output by the MSPI controller..*/
378 /*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
384 /*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
[all …]
Dhp_system_struct.h20 * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
28 * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
32 * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dspi_mem_struct.h41 …1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_D…
42 … /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[…
43 … : 1; /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7…
44 … : 1; /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[…
76 … 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real …
77 …nt32_t reg_aw_size0_1_support_en : 1; /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, M…
99 …ransfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
110 … 1; /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
205 …f_en : 1; /*Set this bit to close AXI read/write transfer to MSPI, which means that o…
243 …In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of…
[all …]
Dxts_aes_reg.h66 /*description: Set this bit to release encrypted result to mspi. This action should only be ass
88 sible to mspi, 3: the encrypted result is visible to mspi..*/
104 /*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
Dspi_mem_reg.h276 /*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
277 is output by the MSPI controller in the second half part of dummy phase. It is u
284 /*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
285 s output by the MSPI controller in the first half part of dummy phase. It is use
292 /*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
293 vel of SPI_IO[7:0] is output by the MSPI controller..*/
299 /*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
300 vel of SPI_DQS is output by the MSPI controller..*/
373 /*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
379 /*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
[all …]
Dhp_system_struct.h20 * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
28 * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
32 * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
Dhp_system_reg.h19 * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
33 * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
40 * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dspi_mem_struct.h89 …uint32_t ecc_skip_page_corner : 1; /*1: MSPI skips page corner when accesses flash. 0…
90 …uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data wi…
92 …ransfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
110 …hold : 1; /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
111 …setup : 1; /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
428 …_err_int_num : 8; /*Set the error times of MSPI ECC read to generate MSPI SPI_ME…
429 …_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when acces…
441 …cc_err_cnt : 8; /*This bits show the error times of MSPI ECC read, including…
449 …m_cs_setup : 1; /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
450 …m_cs_hold : 1; /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
[all …]
Dspi_mem_reg.h301 sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
308 /*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse
315 /*description: 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when acce
456 /*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
462 /*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/
550 /*description: 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is i
1670 /*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
1677 /*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
1686 /*description: These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SP
1696 /*description: This bits show the error times of MSPI ECC read, including ECC byte error and da
[all …]
/hal_espressif-latest/components/spi_flash/
Dflash_ops.c191 //Flash chip requires MSPI specifically, call this function to set them in spi_flash_set_vendor_required_regs()
192 // Set back MSPI registers after Octal PSRAM initialization. in spi_flash_set_vendor_required_regs()
237 * 2. rom code take 0x3f as invalid wp pad num, but take 0 as other invalid mspi pads num in esp_mspi_get_io()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Dmspi_timing_tuning_configs.h26 …* DDR stands for double data rate, MSPI samples at both posedge and negedge. So the real spped wil…
34 * 1. MSPI FLASH and PSRAM share the core clock register. Therefore:
86 * Due to MSPI core clock is used by both MSPI Flash and PSRAM clock,
141 * On 728, MSPI FLASH and PSRAM share the core clock register. Therefore,
Drtc_init.c261 …hange the system clock source to XTAL. Under lower frequency (e.g. XTAL), MSPI timing tuning confi…
270 …* 2. For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning… in calibrate_ocode()
271 * Certain delay will be added to the MSPI RX direction. in calibrate_ocode()
323 …//System clock is switched back to PLL. Here we switch to the MSPI high speed mode, add the delays… in calibrate_ocode()
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/
Drtc_clk_init.c93 …// On ESP32C6, MSPI source clock's default HS divider leads to 120MHz, which is unusable before ca… in rtc_clk_init()
94 …// Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to … in rtc_clk_init()
/hal_espressif-latest/components/spi_flash/esp32s3/
Dopi_flash_private.h30 * @brief Set Octal Flash chip specifically required MSPI register settings here
/hal_espressif-latest/components/esp_system/port/include/
Desp_clk_internal.h26 * After this the MSPI timing tuning can be done.
/hal_espressif-latest/components/esp_psram/esp32s3/
Desp_psram_impl_octal.c265 //Set mspi cs1 drive strength in s_init_psram_pins()
304 //enter MSPI slow mode to init PSRAM device registers in esp_psram_impl_enable()
341 //Flash chip requires MSPI specifically, call this function to set them in esp_psram_impl_enable()

123