1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <assert.h>
9 #include <string.h>
10 #include <stdio.h>
11 #include <sys/param.h> // For MIN/MAX(a, b)
12
13 #include <zephyr/kernel.h>
14 #include <soc/soc.h>
15 #include <soc/soc_memory_layout.h>
16 #include "soc/io_mux_reg.h"
17 #include "sdkconfig.h"
18 #include "esp_attr.h"
19 #include "esp_cpu.h"
20 #include "spi_flash_mmap.h"
21 #include "esp_log.h"
22 #include "esp_private/system_internal.h"
23 #include "esp_private/spi_flash_os.h"
24 #include "esp_private/esp_clk.h"
25 #include "esp_private/esp_gpio_reserve.h"
26 #if CONFIG_IDF_TARGET_ESP32
27 #include "soc_flash_init.h"
28 #include "esp32/rom/cache.h"
29 #include "esp32/rom/spi_flash.h"
30 #elif CONFIG_IDF_TARGET_ESP32S2
31 #include "esp32s2/rom/cache.h"
32 #elif CONFIG_IDF_TARGET_ESP32S3
33 #include "soc/spi_mem_reg.h"
34 #include "esp32s3/rom/opi_flash.h"
35 #include "esp32s3/rom/cache.h"
36 #include "esp32s3/opi_flash_private.h"
37 #elif CONFIG_IDF_TARGET_ESP32C3
38 #include "esp32c3/rom/cache.h"
39 #elif CONFIG_IDF_TARGET_ESP32C2
40 #include "esp32c2/rom/cache.h"
41 #elif CONFIG_IDF_TARGET_ESP32C6
42 #include "esp32c6/rom/cache.h"
43 #endif
44 #include "esp_rom_spiflash.h"
45 #include "esp_flash_partitions.h"
46 #include "esp_private/mspi_timing_tuning.h"
47 #include "esp_private/cache_utils.h"
48 #include "esp_flash.h"
49 #include "esp_attr.h"
50 #include "bootloader_flash.h"
51 #include "bootloader_flash_config.h"
52 #include "esp_compiler.h"
53 #include "esp_rom_efuse.h"
54 #if CONFIG_SPIRAM
55 #include "esp_private/esp_psram_io.h"
56 #endif
57 #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
58 #include "hal/cache_hal.h"
59 #endif
60
61 /* bytes erased by SPIEraseBlock() ROM function */
62 #define BLOCK_ERASE_SIZE 65536
63
64 /* Limit number of bytes written/read in a single SPI operation,
65 as these operations disable all higher priority tasks from running.
66 */
67 #ifdef CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
68 #define MAX_WRITE_CHUNK CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
69 #else
70 #define MAX_WRITE_CHUNK 8192
71 #endif // CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
72
73 #define MAX_READ_CHUNK 16384
74
75 static const char *TAG __attribute__((unused)) = "spi_flash";
76
77 const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_default_ops = {
78 .start = spi_flash_disable_interrupts_caches_and_other_cpu,
79 .end = spi_flash_enable_interrupts_caches_and_other_cpu,
80 };
81
82 const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_no_os_ops = {
83 .start = spi_flash_disable_interrupts_caches_and_other_cpu_no_os,
84 .end = spi_flash_enable_interrupts_caches_no_os,
85 };
86
87 static const spi_flash_guard_funcs_t *s_flash_guard_ops;
88
spi_flash_guard_set(const spi_flash_guard_funcs_t * funcs)89 void IRAM_ATTR spi_flash_guard_set(const spi_flash_guard_funcs_t *funcs)
90 {
91 s_flash_guard_ops = funcs;
92 }
93
spi_flash_guard_get(void)94 const spi_flash_guard_funcs_t *IRAM_ATTR spi_flash_guard_get(void)
95 {
96 return s_flash_guard_ops;
97 }
98
99
100 #ifdef CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
101 #define UNSAFE_WRITE_ADDRESS abort()
102 #else
103 #define UNSAFE_WRITE_ADDRESS return false
104 #endif
105
106
is_safe_write_address(size_t addr,size_t size)107 static __attribute__((unused)) bool is_safe_write_address(size_t addr, size_t size)
108 {
109 if (!esp_partition_main_flash_region_safe(addr, size)) {
110 UNSAFE_WRITE_ADDRESS;
111 }
112 return true;
113 }
114
115 #if CONFIG_SPI_FLASH_ROM_IMPL
116 #include "esp_heap_caps.h"
117
spi_flash_malloc_internal(size_t size)118 void IRAM_ATTR *spi_flash_malloc_internal(size_t size)
119 {
120 return heap_caps_malloc(size, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
121 }
122
spi_flash_rom_impl_init(void)123 void IRAM_ATTR spi_flash_rom_impl_init(void)
124 {
125 spi_flash_guard_set(&g_flash_guard_default_ops);
126
127 /* These two functions are in ROM only */
128 extern void spi_flash_mmap_os_func_set(void *(*func1)(size_t size), void (*func2)(void *p));
129 spi_flash_mmap_os_func_set(spi_flash_malloc_internal, heap_caps_free);
130
131 extern esp_err_t spi_flash_mmap_page_num_init(uint32_t page_num);
132 spi_flash_mmap_page_num_init(128);
133 }
134 #endif
135
esp_mspi_pin_init(void)136 void IRAM_ATTR esp_mspi_pin_init(void)
137 {
138 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
139 bool octal_mspi_required = bootloader_flash_is_octal_mode_enabled();
140 #if CONFIG_SPIRAM_MODE_OCT
141 octal_mspi_required |= true;
142 #endif
143
144 if (octal_mspi_required) {
145 esp_rom_opiflash_pin_config();
146 mspi_timing_set_pin_drive_strength();
147 }
148 //Set F4R4 board pin drive strength. TODO: IDF-3663
149 #endif
150 /* Reserve the GPIO pins */
151 uint64_t reserve_pin_mask = 0;
152 uint8_t mspi_io;
153 for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
154 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
155 if (!bootloader_flash_is_octal_mode_enabled()
156 && i >= ESP_MSPI_IO_DQS && i <= ESP_MSPI_IO_D7) {
157 continue;
158 }
159 #endif
160 mspi_io = esp_mspi_get_io(i);
161 if (mspi_io < 64) { // 'reserve_pin_mask' have 64 bits length
162 reserve_pin_mask |= BIT64(mspi_io);
163 }
164 }
165 esp_gpio_reserve_pins(reserve_pin_mask);
166 }
167
spi_flash_set_rom_required_regs(void)168 void IRAM_ATTR spi_flash_set_rom_required_regs(void)
169 {
170 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
171 if (bootloader_flash_is_octal_mode_enabled()) {
172 //Disable the variable dummy mode when doing timing tuning
173 CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
174 /**
175 * STR /DTR mode setting is done every time when `esp_rom_opiflash_exec_cmd` is called
176 *
177 * Add any registers that are not set in ROM SPI flash functions here in the future
178 */
179 }
180 #endif
181 }
182
183 #if CONFIG_SPIRAM_MODE_OCT
184 // This function will only be called when Octal PSRAM enabled.
spi_flash_set_vendor_required_regs(void)185 void IRAM_ATTR spi_flash_set_vendor_required_regs(void)
186 {
187 if (bootloader_flash_is_octal_mode_enabled()) {
188 esp_opiflash_set_required_regs();
189 SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 1, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
190 } else {
191 //Flash chip requires MSPI specifically, call this function to set them
192 // Set back MSPI registers after Octal PSRAM initialization.
193 SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 0, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
194 }
195 }
196 #endif
197
198 static const uint8_t s_mspi_io_num_default[] = {
199 SPI_CLK_GPIO_NUM,
200 SPI_Q_GPIO_NUM,
201 SPI_D_GPIO_NUM,
202 SPI_CS0_GPIO_NUM,
203 SPI_HD_GPIO_NUM,
204 SPI_WP_GPIO_NUM,
205 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
206 SPI_DQS_GPIO_NUM,
207 SPI_D4_GPIO_NUM,
208 SPI_D5_GPIO_NUM,
209 SPI_D6_GPIO_NUM,
210 SPI_D7_GPIO_NUM
211 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
212 };
213
esp_mspi_get_io(esp_mspi_io_t io)214 uint8_t esp_mspi_get_io(esp_mspi_io_t io)
215 {
216 #if CONFIG_SPIRAM
217 if (io == ESP_MSPI_IO_CS1) {
218 return esp_psram_io_get_cs_io();
219 }
220 #endif
221
222 assert(io >= ESP_MSPI_IO_CLK);
223 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
224 assert(io <= ESP_MSPI_IO_D7);
225 #else
226 assert(io <= ESP_MSPI_IO_WP);
227 #endif
228
229 #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
230 uint8_t mspi_io = 0;
231 uint32_t spiconfig = 0;
232
233 if (io == ESP_MSPI_IO_WP) {
234 /**
235 * wp pad is a bit special:
236 * 1. since 32's efuse does not have enough bits for wp pad, so wp pad config put in flash bin header
237 * 2. rom code take 0x3f as invalid wp pad num, but take 0 as other invalid mspi pads num
238 */
239 #if CONFIG_IDF_TARGET_ESP32
240 return flash_get_wp_pin();
241 #else
242 spiconfig = esp_rom_efuse_get_flash_wp_gpio();
243 return (spiconfig == 0x3f) ? s_mspi_io_num_default[io] : spiconfig & 0x3f;
244 #endif
245 }
246
247 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
248 spiconfig = (io < ESP_MSPI_IO_WP) ? esp_rom_efuse_get_flash_gpio_info() : esp_rom_efuse_get_opiconfig();
249 #else
250 spiconfig = esp_rom_efuse_get_flash_gpio_info();
251 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
252
253 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
254 mspi_io = s_mspi_io_num_default[io];
255 } else if (io < ESP_MSPI_IO_WP) {
256 /**
257 * [0 : 5] -- CLK
258 * [6 :11] -- Q(D1)
259 * [12:17] -- D(D0)
260 * [18:23] -- CS
261 * [24:29] -- HD(D3)
262 */
263 mspi_io = (spiconfig >> io * 6) & 0x3f;
264 }
265 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
266 else {
267 /**
268 * [0 : 5] -- DQS
269 * [6 :11] -- D4
270 * [12:17] -- D5
271 * [18:23] -- D6
272 * [24:29] -- D7
273 */
274 mspi_io = (spiconfig >> (io - ESP_MSPI_IO_DQS) * 6) & 0x3f;
275 }
276 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
277 return mspi_io;
278 #else // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
279 return s_mspi_io_num_default[io];
280 #endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
281 }
282
283 #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
284
spi_flash_set_clock_src(soc_periph_mspi_clk_src_t clk_src)285 IRAM_ATTR void spi_flash_set_clock_src(soc_periph_mspi_clk_src_t clk_src)
286 {
287 cache_hal_freeze(CACHE_TYPE_INSTRUCTION);
288 spimem_flash_ll_set_clock_source(clk_src);
289 cache_hal_unfreeze(CACHE_TYPE_INSTRUCTION);
290 }
291 #endif // SOC_MEMSPI_CLOCK_IS_INDEPENDENT
292
