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/Zephyr-latest/dts/bindings/memory-controllers/
Dst,stm32-fmc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Flexible Memory Controller (FMC).
7 The FMC allows to interface with static-memory mapped external devices such as
11 controller. Each external device is accessed by means of a unique chip select.
14 The flexible memory controller includes three memory controllers:
16 - NOR/PSRAM memory controller
17 - NAND memory controller (some devices also support PC Card)
18 - Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
20 Each memory controller is defined below the FMC DeviceTree node and is managed
27 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
[all …]
Dst,stm32h7-fmc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Flexible Memory Controller (FMC).
7 The FMC allows to interface with static-memory mapped external devices such as
11 controller. Each external device is accessed by means of a unique chip select.
14 The flexible memory controller includes three memory controllers:
16 - NOR/PSRAM memory controller
17 - NAND memory controller (some devices also support PC Card)
18 - Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
20 Each memory controller is defined below the FMC DeviceTree node and is managed
27 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
[all …]
Dst,stm32-fmc-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Flexible Memory Controller (SDRAM controller).
7 The FMC SDRAM controller can be used to interface with external SDRAM
13 The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
15 bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
20 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
25 power-up-delay = <100>;
26 num-auto-refresh = <8>;
27 mode-register = <0x220>;
28 refresh-rate = <603>;
[all …]
Dst,stm32-fmc-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Flexible Memory Controller (NOR Flash/PSRAM/SRAM controller).
11 - 8 bits
12 - 16 bits
13 - 32 bits
15 - Asynchronous mode
16 - Burst mode for synchronous accesses with configurable option to split burst
18 - Multiplexed or non-multiplexed
19 * NOR Flash memory
20 - Asynchronous mode
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/Zephyr-latest/include/zephyr/drivers/pcie/
Dcontroller.h10 * SPDX-License-Identifier: Apache-2.0
23 * @brief PCI Express Controller Interface
24 * @defgroup pcie_controller_interface PCI Express Controller Interface
34 * @brief Function called to read a 32-bit word from an endpoint's configuration space.
36 * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
37 * configuration space access method (I/O port, memory mapped or custom method)
39 * @param dev PCI Express Controller device pointer
48 * @brief Function called to write a 32-bit word to an endpoint's configuration space.
50 * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
51 * configuration space access method (I/O port, memory mapped or custom method)
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/Zephyr-latest/dts/bindings/flash_controller/
Dnordic,rram-controller.yaml4 # SPDX-License-Identifier: Apache-2.0
8 Nordic RRAMC (Resistive random access memory controller)
10 The resistive random access memory controller (RRAMC) is used for writing
11 the internal RRAM memory, the secure information configuration registers (SICR),
14 compatible: "nordic,rram-controller"
Dgd,gd32-flash-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
7 GD32 FMC v1: its flash memory has 1 bank, page size is equal in the bank,
10 GD32 FMC v2: its flash memory has 2 banks. Page size equal within the same bank but
14 GD32 FMC v3: its flash memory has 2 banks, use sector size as the minimum operating
17 compatible: "gd,gd32-flash-controller"
19 include: flash-controller.yaml
/Zephyr-latest/dts/bindings/mtd/
Dst,stm32-nv-flash.yaml2 STM32 flash memory. This binding is for the flash memory itself, not
3 the flash controller peripheral. For that, see the
4 "st,stm32-flash-controller" binding.
6 include: soc-nv-flash.yaml
8 compatible: st,stm32-nv-flash
11 max-erase-time:
13 description: max erase time(millisecond) of a flash sector or page or half-page
15 bank2-flash-size:
18 Embedded flash memory bank 2 size in KBytes.
19 Used by CM4 CPU because it cannot access flash controller register to read size.
[all …]
/Zephyr-latest/drivers/memc/
DKconfig.stm322 # SPDX-License-Identifier: Apache-2.0
5 bool "STM32 Flexible Memory Controller (FMC)"
10 Enable STM32 Flexible Memory Controller.
15 bool "STM32 FMC SDRAM controller"
21 Enable STM32 FMC SDRAM controller.
24 bool "STM32 FMC NOR/PSRAM controller"
31 Enable STM32 FMC NOR/PSRAM controller.
DKconfig1 # Memory controller configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Memory controller drivers [EXPERIMENTAL]"
10 Add support for memory controllers
19 Memory controllers initialization priority.
38 module-str = memc
DKconfig.sam2 # SPDX-License-Identifier: Apache-2.0
5 bool "Atmel Static Memory Controller (SMC)"
10 Enable Atmel Static Memory Controller.
DKconfig.sifive2 # SPDX-License-Identifier: Apache-2.0
5 bool "HiFive Unmatched DRAM Memory Controller"
9 Enable HiFive Unmatched Memory Controller.
DKconfig.smartbond4 # SPDX-License-Identifier: Apache-2.0
7 bool "Smartbond NOR/PSRAM memory controller"
11 Enable Smartbond NOR/PSRAM memory controller.
/Zephyr-latest/dts/bindings/dma/
Despressif,esp32-gdma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Espressif's GDMA (General Direct Memory Access) Node
7 General Direct Memory Access (GDMA) is a feature that allows
8 peripheral-to-memory, memory-to-peripheral, and memory-to-memory
11 The GDMA controller in ESP32-C3 has six independent channels,
24 The GDMA controller in ESP32-S3 has ten independent channels,
40 compatible: "espressif,esp32-gdma"
42 include: dma-controller.yaml
45 "#dma-cells":
48 dma-cells:
[all …]
Dst,stm32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
11 or V2 like stm32L4 soc or stm322WB, some also have DMAMUX controller
14 compatible: "st,stm32-dma"
16 include: dma-controller.yaml
27 description: If the DMA controller V1 supports memory to memory transfer
29 dma-offset:
Dbrcm,iproc-pax-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 1
6 include: dma-controller.yaml
8 compatible: brcm,iproc-pax-dma-v1
13 Register space for the memory mapped PAX DMA controller registers,
17 bd-memory:
19 description: Uncached memory address to populate dma buffer descriptors
21 scr-addr-loc:
25 scr-size-loc:
32 pcie-ep:
Dbrcm,iproc-pax-dma-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 2
6 include: dma-controller.yaml
8 compatible: brcm,iproc-pax-dma-v2
13 Register space for the memory mapped PAX DMA controller registers,
17 bd-memory:
19 description: Uncached memory address to populate dma buffer descriptors
21 scr-addr-loc:
25 scr-size-loc:
32 pcie-ep:
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 BDMA controller
7 The STM32 BDMA is a general-purpose direct memory access controller
10 BDMA clients connected to the STM32 BDMA controller must use the format
11 described in the dma.txt file, using a four-cell specifier for each
12 channel: a phandle to the BDMA controller plus the following four integer cells:
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
[all …]
Ddma-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
11 "#dma-cells":
16 dma-channel-mask:
23 dma-channels:
25 description: Number of DMA channels supported by the controller
27 dma-requests:
29 description: Number of DMA request signals supported by the controller.
31 dma-buf-addr-alignment:
33 description: Memory address alignment requirement for DMA buffers used by the controller.
35 dma-buf-size-alignment:
[all …]
Dgd,gd32-dma-base.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: dma-controller.yaml
13 dma-channels:
21 description: The DMA controller supporting memory to memory transfer
/Zephyr-latest/boards/gaisler/gr716a_mini/doc/
Dindex.rst6 The GR716-MINI development board provides:
37 The application is linked to the on-chip tightly coupled memory by
45 .. code-block:: console
47 $ grmon -u -cginit 0x00010000 -uart /dev/ttyUSB0
50 Copyright (C) 2020 Cobham Gaisler - All rights reserved.
52 Comments or bug-reports to support@gaisler.com
60 AHB-to-AHB Bridge Cobham Gaisler
61 MIL-STD-1553B Interface Cobham Gaisler
65 CAN Controller with DMA Cobham Gaisler
66 CAN Controller with DMA Cobham Gaisler
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/Zephyr-latest/boards/mediatek/mt8196/
Dmt8196_adsp.dts2 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #address-cells = <1>;
10 #size-cells = <1>;
12 sram0: memory@4e100000 {
13 device_type = "memory";
14 compatible = "mmio-sram";
18 dram0: memory@90000000 {
19 device_type = "memory";
20 compatible = "mmio-sram";
[all …]
/Zephyr-latest/modules/
DKconfig.stm324 # SPDX-License-Identifier: Apache-2.0
25 Enable STM32Cube Analog-to-Digital Converter (ADC) HAL module driver
30 Enable STM32Cube Extended Analog-to-Digital Converter (ADC) HAL
36 Enable STM32Cube Controller Area Network (CAN) HAL module driver
41 Enable STM32Cube HDMI-CEC controller (CEC) HAL module driver
52 Enable STM32Cube CORDIC co-processor (CORDIC) functions HAL module
86 Enable STM32Cube Digital-to-analog converter (DAC) HAL module driver
91 Enable STM32Cube Extended Digital-to-analog converter (DAC) HAL module
125 Enable STM32Cube Direct Memory Access controller (DMA) HAL module
131 Enable STM32Cube Chrom-Art Accelerator™ controller (DMA2D) HAL module
[all …]
/Zephyr-latest/dts/arm/ti/
Dj721e_main_r5.dtsi6 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv7-r.dtsi>
12 #include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-r5";
29 atcm: memory@0 {
30 device_type = "memory";
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_ke17z.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &sram_l;
10 /delete-node/ &sram_u;
14 zephyr,flash-controller = &ftfa;
18 sram_l: memory@1fffc000 {
19 compatible = "zephyr,memory-region", "mmio-sram";
21 zephyr,memory-region = "SRAML";
24 sram_u: memory@20000000 {
25 compatible = "zephyr,memory-region", "mmio-sram";
27 zephyr,memory-region = "SRAMU";
[all …]

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