Lines Matching +full:memory +full:- +full:controller
10 * SPDX-License-Identifier: Apache-2.0
23 * @brief PCI Express Controller Interface
24 * @defgroup pcie_controller_interface PCI Express Controller Interface
34 * @brief Function called to read a 32-bit word from an endpoint's configuration space.
36 * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
37 * configuration space access method (I/O port, memory mapped or custom method)
39 * @param dev PCI Express Controller device pointer
48 * @brief Function called to write a 32-bit word to an endpoint's configuration space.
50 * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
51 * configuration space access method (I/O port, memory mapped or custom method)
53 * @param dev PCI Express Controller device pointer
62 * @brief Function called to allocate a memory region subset for an endpoint Base Address Register.
64 * When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
65 * via the Base Address Registers from I/O or Memory types.
67 * This call allocates such zone in the PCI Express Controller memory regions if
70 * @param dev PCI Express Controller device pointer
72 * @param mem True if the BAR is of memory type
73 * @param mem64 True if the BAR is of 64bit memory type
75 * @param bar_bus_addr bus-centric address allocated to be written in the BAR register
83 * @brief Function called to get the current allocation base of a memory region subset
86 * When enumerating PCIe Endpoints, Type1 bridge endpoints requires a range of memory
89 * @param dev PCI Express Controller device pointer
91 * @param mem True if the BAR is of memory type
92 * @param mem64 True if the BAR is of 64bit memory type
94 * @param bar_base_addr bus-centric address allocation base
102 * @brief Function called to translate an endpoint Base Address Register bus-centric address
105 * When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
106 * via the Base Address Registers from I/O or Memory types.
108 * The bus-centric address set in this BAR register is not necessarily accessible from the CPU,
109 * thus must be translated by using the PCI Express Controller memory regions translation
112 * @param dev PCI Express Controller device pointer
114 * @param mem True if the BAR is of memory type
115 * @param mem64 True if the BAR is of 64bit memory type
116 * @param bar_bus_addr bus-centric address written in the BAR register
117 * @param bar_addr CPU-centric address translated from the bus-centric address
130 * @brief Read a 32-bit word from a Memory-Mapped endpoint's configuration space.
132 * Read a 32-bit word from an endpoint's configuration space from a Memory-Mapped
136 * @param cfg_addr Logical address of Memory-Mapped configuration space
145 * @brief Write a 32-bit word to a Memory-Mapped endpoint's configuration space.
147 * Write a 32-bit word to an endpoint's configuration space from a Memory-Mapped
151 * @param cfg_addr Logical address of Memory-Mapped configuration space
163 * When on non-x86 architecture or when firmware didn't setup the PCIe Bus hierarchy,
166 * @param dev PCI Express Controller device pointer
172 * that supports the PCI Express Controller API
186 * @brief Read a 32-bit word from an endpoint's configuration space.
188 * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
189 * configuration space access method (I/O port, memory mapped or custom method)
191 * @param dev PCI Express Controller device pointer
200 (const struct pcie_ctrl_driver_api *)dev->api; in pcie_ctrl_conf_read()
202 return api->conf_read(dev, bdf, reg); in pcie_ctrl_conf_read()
206 * @brief Write a 32-bit word to an endpoint's configuration space.
208 * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
209 * configuration space access method (I/O port, memory mapped or custom method)
211 * @param dev PCI Express Controller device pointer
220 (const struct pcie_ctrl_driver_api *)dev->api; in pcie_ctrl_conf_write()
222 api->conf_write(dev, bdf, reg, data); in pcie_ctrl_conf_write()
226 * @brief Allocate a memory region subset for an endpoint Base Address Register.
228 * When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
229 * via the Base Address Registers from I/O or Memory types.
231 * This call allocates such zone in the PCI Express Controller memory regions if
234 * @param dev PCI Express Controller device pointer
236 * @param mem True if the BAR is of memory type
237 * @param mem64 True if the BAR is of 64bit memory type
239 * @param bar_bus_addr bus-centric address allocated to be written in the BAR register
247 (const struct pcie_ctrl_driver_api *)dev->api; in pcie_ctrl_region_allocate()
249 return api->region_allocate(dev, bdf, mem, mem64, bar_size, bar_bus_addr); in pcie_ctrl_region_allocate()
253 * @brief Function called to get the current allocation base of a memory region subset
256 * When enumerating PCIe Endpoints, Type1 bridge endpoints requires a range of memory
259 * @param dev PCI Express Controller device pointer
261 * @param mem True if the BAR is of memory type
262 * @param mem64 True if the BAR is of 64bit memory type
264 * @param bar_base_addr bus-centric address allocation base
272 (const struct pcie_ctrl_driver_api *)dev->api; in pcie_ctrl_region_get_allocate_base()
274 return api->region_get_allocate_base(dev, bdf, mem, mem64, align, bar_base_addr); in pcie_ctrl_region_get_allocate_base()
278 * @brief Translate an endpoint Base Address Register bus-centric address into Physical address.
280 * When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
281 * via the Base Address Registers from I/O or Memory types.
283 * The bus-centric address set in this BAR register is not necessarily accessible from the CPU,
284 * thus must be translated by using the PCI Express Controller memory regions translation
287 * @param dev PCI Express Controller device pointer
289 * @param mem True if the BAR is of memory type
290 * @param mem64 True if the BAR is of 64bit memory type
291 * @param bar_bus_addr bus-centric address written in the BAR register
292 * @param bar_addr CPU-centric address translated from the bus-centric address
300 (const struct pcie_ctrl_driver_api *)dev->api; in pcie_ctrl_region_translate()
302 if (!api->region_translate) { in pcie_ctrl_region_translate()
306 return api->region_translate(dev, bdf, mem, mem64, bar_bus_addr, bar_addr); in pcie_ctrl_region_translate()
315 (const struct pcie_ctrl_driver_api *)dev->api; in pcie_ctrl_msi_device_setup()
317 return api->msi_device_setup(dev, priority, vectors, n_vector); in pcie_ctrl_msi_device_setup()
321 /** @brief Structure describing a device that supports the PCI Express Controller API
335 /* Flags as defined in the PCI Bus Binding to IEEE Std 1275-1994 */
337 /* bus-centric offset from the start of the region */
339 /* CPU-centric offset from the start of the region */