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/Zephyr-latest/arch/arm/core/mpu/
DKconfig1 # Memory Protection Unit (MPU) configuration options
4 # SPDX-License-Identifier: Apache-2.0
20 MCU implements Memory Protection Unit.
23 The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
24 alignment of MPU region base address and size.
26 The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
27 to have power-of-two alignment for base address and region size.
29 The ARMv8-M MPU requires the active MPU regions be non-overlapping.
30 As a result of this, the ARMv8-M MPU needs to fully partition the
31 memory map when programming dynamic memory regions (e.g. PRIV stack
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/Zephyr-latest/dts/bindings/mtd/
Dnxp,s32-qspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
5 QSPI memory device supporting xSPI or Hyperbus.
7 compatible: "nxp,s32-qspi-device"
11 on-bus: qspi
17 memory-alignment:
20 Memory alignment in bytes, used to calculate padding when performing
22 If not provided, 1 byte alignment will be selected.
/Zephyr-latest/arch/arm64/core/cortex_r/
DKconfig1 # Memory Protection Unit (MPU) configuration options
6 # SPDX-License-Identifier: Apache-2.0
18 MPU implements Memory Protection Unit.
21 The ARMv8-R MPU architecture requires a power-of-two alignment
24 The ARMv8-R MPU requires the active MPU regions be non-overlapping.
25 As a result of this, the ARMv8-R MPU needs to fully partition the
26 memory map when programming dynamic memory regions (e.g. PRIV stack
27 guard, user thread stack, and application memory domains), if the
29 of the ARMv8-R background memory map. The application developer may
30 enforce full PRIV (kernel) memory partition by enabling the
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/Zephyr-latest/include/zephyr/debug/
Dgdbstub.h4 * SPDX-License-Identifier: Apache-2.0
18 /* Access permissions for memory regions */
29 /** Describe one memory region */
31 /** Start address of a memory region */
34 /** End address of a memory region */
37 /** Memory region attributes */
40 /** Read/write alignment, 0 if using default alignment */
41 uint8_t alignment; member
54 * Memory region descriptions used for GDB memory access.
56 * This array specifies which region of memory GDB can access
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/Zephyr-latest/drivers/dma/
DKconfig.nxp_sof_host_dma2 # SPDX-License-Identifier: Apache-2.0
14 memory and firmware (local) memory, which
21 int "Alignment (in bytes) required for memory regions passed to this driver"
24 Use this to set the alignment (in bytes)
26 this driver to adjust a memory region's size
30 no alignment restrictions imposed by memcpy.
DKconfig.nxp_edma2 # SPDX-License-Identifier: Apache-2.0
5 bool "NXP enhanced Direct Memory Access (eDMA) driver"
14 int "Alignment (in bytes) required for the transfers"
17 Use this to set the alignment (in bytes)
19 adjust the addresses and sizes of the memory
/Zephyr-latest/tests/drivers/display/display_read_write/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
9 bool "Place the display buffer in a specific memory section"
11 Place the display buffer in a specific memory section.
14 int "Display buffer memory alignment"
17 Specific display buffer alignment.
22 string "Memory section to place Display Buffer"
24 Specific memory section to place the display buffer.
/Zephyr-latest/dts/bindings/dma/
Ddma-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
11 "#dma-cells":
16 dma-channel-mask:
23 dma-channels:
27 dma-requests:
31 dma-buf-addr-alignment:
33 description: Memory address alignment requirement for DMA buffers used by the controller.
35 dma-buf-size-alignment:
37 description: Memory size alignment requirement for DMA buffers used by the controller.
39 dma-copy-alignment:
/Zephyr-latest/dts/bindings/ipc/
Dzephyr,ipc-icmsg.yaml4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "zephyr,ipc-icmsg"
14 tx-region:
15 description: phandle to the shared memory region used for data transmission
19 rx-region:
20 description: phandle to the shared memory region used for data reception
24 dcache-alignment:
27 Data cache alignment. If any side of the communication uses cache on
28 rx-region/tx-region this property must be the biggest value of the
29 invalidation or the write-back size for both sides of the communication.
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/Zephyr-latest/include/zephyr/mem_mgmt/
Dmem_attr_heap.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Memory heaps based on memory attributes
12 * @defgroup memory_attr_heap Memory heaps based on memory attributes
24 * @brief Init the memory pool
26 * This must be the first function to be called to initialize the memory pools
27 * from all the memory regions with the a software attribute.
30 * @retval -EALREADY if the pool was already initialized.
31 * @retval -ENOMEM too many regions already allocated.
36 * @brief Allocate memory with a specified attribute and size.
38 * Allocates a block of memory of the specified size in bytes and with a
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/Zephyr-latest/doc/services/ipc/ipc_service/backends/
Dipc_service_icmsg.rst8 memory footprint. The ICMsg backend is build on top of :ref:`spsc_pbuf`.
13 The ICMsg backend uses shared memory and MBOX devices for exchanging data.
14 Shared memory is used to store the data, MBOX devices are used to signal that
27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
28 …This must be the largest value of the invalidation or the write-back size for both sides of the co…
29 You can skip it if none of the communication sides is using data cache on shared memory.
30 * Define two memory regions and assign them to ``tx-region`` and ``rx-region``
31 of an instance. Ensure that the memory regions used for data exchange are
40 Make sure that you set correct value of the ``dcache-alignment``.
46 .. code-block:: devicetree
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Dipc_service_icbmsg.rst7 Data transferred over this backend travels in dynamically allocated buffers on shared memory.
11 …ming some common problems with other backends (mostly related to multithread access and zero-copy).
17 The shared memory is divided into two parts.
18 One is reserved for the ICMsg and the other contains equal-sized blocks.
26 For the zero-copy case, this is done by the caller, otherwise, it is copied automatically.
43 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
44 …This must be the largest value of the invalidation or the write-back size for both sides of the co…
45 You can skip it if none of the communication sides is using data cache on shared memory.
46 * Define two memory regions and assign them to ``tx-region`` and ``rx-region`` of an instance.
47 …Ensure that the memory regions used for data exchange are unique (not overlapping any other region…
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/Zephyr-latest/include/zephyr/sys/
Dmulti_heap.h2 * SPDX-License-Identifier: Apache-2.0
13 * @defgroup multi_heap_wrapper Multi-Heap Wrapper
19 * @brief Multi-heap allocator
22 * separately managed pools of memory that must be accessed via a
29 * in backend, which is then provided to a user-specified "choice"
36 * @brief Multi-heap choice function
38 * This is a user-provided functions whose responsibility is selecting
43 * allocation, and may choose to pad the user-provided values as
50 * @param mheap Multi-heap structure.
51 * @param cfg An opaque user-provided value. It may be interpreted in
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Dsys_heap.h4 * SPDX-License-Identifier: Apache-2.0
22 * power-of-two buckets.
26 * bytes for heaps >256kb or on 64 bit systems), plus a log2-sized
27 * array of 2-word bucket headers. No coarse alignment restrictions
31 * Simple API. Initialize at runtime with any blob of memory and not
32 * a macro-generated, carefully aligned static array. Allocate and
38 * to the smallest block guaranteed to fit. Split memory remaining in
44 * that has a compile-time-configurable upper bound, setting this to
52 * runtime lives in the heap memory itself and this struct simply
83 * @return -EINVAL if null pointers, otherwise 0
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/Zephyr-latest/soc/andestech/ae350/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
89 a look-up table and replaces suitable 32-bit instructions with
90 the 16-bit "exec.it <INDEX>".
93 bool "Andes V5 Physical Memory Attribute (PMA)"
99 configure physical memory attribute by PMA CSRs. The address
100 matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
101 (power-of-two alignment).
108 Minimum size (and alignment) of an PMA region. Use this symbol
109 to guarantee minimum size and alignment of PMA regions.
120 between cache and external non-caching master, such as DMA
/Zephyr-latest/modules/lvgl/
DKconfig.memory1 # Copyright (c) 2018-2019 Jan Van Winkel <jan.van_winkel@dxplore.eu>
3 # SPDX-License-Identifier: Apache-2.0
5 menu "Memory manager settings"
20 prompt "Memory pool"
23 Memory pool to use for lvgl allocated objects
35 Use a dedicated memory pool from a private sys heap.
40 int "Memory pool size"
44 Size of the memory pool in bytes
47 bool "Link memory pool to custom section"
50 Place LVGL memory pool in custom section, with tag ".lvgl_heap".
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/Zephyr-latest/lib/net_buf/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
21 module-str = net_buf
37 bool "Network buffer memory debugging"
53 int "Network buffer alignment restriction"
56 Alignment restriction for network buffers. This is useful for
59 Default value of 0 means the alignment will be the size of a void pointer,
60 any other value will force the alignment of a net buffer in bytes.
/Zephyr-latest/include/zephyr/kernel/
Dthread_stack.h4 * SPDX-License-Identifier: Apache-2.0
63 * to the CPU and ABI requirements. This is not used for any memory protection
79 * all the data members that are pre-populated in arch_new_thread().
89 (type *)((ptr) - sizeof(type))
122 * @param size Size of the stack memory region
136 * @param size Size of the stack memory region
150 * @param size Size of the stack memory region
157 * @brief Define a toplevel kernel stack memory region in specified section
159 * This defines a region of memory for use as a thread stack in
168 * The total amount of memory allocated may be increased to accommodate
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/Zephyr-latest/subsys/debug/gdbstub/
Dgdbstub.c4 * SPDX-License-Identifier: Apache-2.0
41 /* Empty memory region array */
44 /* Number of memory regions */
48 * Given a starting address and length of a memory block, find a memory
49 * region descriptor from the memory region array where the memory block
50 * fits inside the memory region.
52 * @param addr Starting address of the memory block
53 * @param len Length of the memory block
55 * @return Pointer to the memory region description if found.
61 #pragma GCC diagnostic ignored "-Warray-bounds"
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/Zephyr-latest/include/zephyr/drivers/usb/
Dudc_buf.h4 * SPDX-License-Identifier: Apache-2.0
20 * Here we try to get DMA-safe buffers, but we lack a consistent source of
22 * consistent source of information about what part of memory is DMA'able.
23 * For now, we simply assume that all available memory is DMA'able and use
24 * Kconfig option DCACHE_LINE_SIZE for alignment and granularity.
30 * Default alignment and granularity to pointer size if the platform does not
31 * have a data cache or buffers are placed in nocache memory region.
46 /** Buffer alignment required by the UDC driver */
53 * @brief Define a UDC driver-compliant static buffer
95 * @brief Define a new pool for UDC buffers with variable-size payloads
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/Zephyr-latest/include/zephyr/app_memory/
Dmem_domain.h3 * Copyright (c) 2018-2020 Intel Corporation
5 * SPDX-License-Identifier: Apache-2.0
22 * @defgroup mem_domain_apis Memory domain APIs
31 * @brief Statically declare a memory partition
45 * @brief Memory Partition
47 * A memory partition is a region of memory in the linear address space
50 * The alignment of the starting address, and the alignment of the size
52 * underlying memory management hardware; arbitrary values are unlikely
56 /** start address of memory partition */
58 /** size of memory partition */
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/Zephyr-latest/lib/heap/
DKconfig3 # SPDX-License-Identifier: Apache-2.0
5 menu "Heap and Memory Allocation"
14 environments that require sensitive detection of memory
60 such as memory allocation and de-allocation.
75 Heaps using reduced-size chunk headers can accommodate so called
78 Heaps using full-size chunk headers can have a total size up to
81 On 32-bit system the tradeoff is selectable between:
83 - "small" heaps with low memory and runtime overhead;
85 - "big" heaps with bigger memory overhead even for small heaps;
87 - "auto" providing optimal memory overhead in all cases but with
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/Zephyr-latest/samples/subsys/ipc/ipc_service/icmsg/boards/
Dnrf54l15dk_nrf54l15_cpuapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 reserved-memory {
10 #address-cells = <1>;
11 #size-cells = <1>;
13 sram_rx: memory@20018000 {
17 sram_tx: memory@20020000 {
25 compatible = "zephyr,ipc-icmsg";
26 dcache-alignment = <32>;
27 tx-region = <&sram_tx>;
28 rx-region = <&sram_rx>;
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/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_ace15_mtpm.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
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/Zephyr-latest/arch/arm/core/mmu/
DKconfig2 # ARMv7 Memory Management Unit (MMU) configuration options
5 # SPDX-License-Identifier: Apache-2.0
11 bool "ARMv7 Cortex-A MMU Support"
18 The current CPU has an ARMv7 Memory Management Unit.
32 Minimum size (and alignment) of an ARM MMU page.

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