Searched +full:max +full:- +full:speed (Results 1 – 25 of 358) sorted by relevance
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | wch,afio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
13 "#address-cells":
16 "#size-cells":
20 child-binding:
23 child-binding:
28 - name: pincfg-node.yaml
29 property-allowlist:
30 - bias-high-impedance
31 - bias-pull-up
32 - bias-pull-down
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| D | gd,gd32-pinctrl-afio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required). Only
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| D | gd,gd32-pinctrl-af.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required).
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| D | st,stm32f1-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
27 - "disable"
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| /Zephyr-latest/tests/drivers/pinctrl/gd32/boards/ |
| D | gd32f450i_eval.overlay | 3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "vnd,pinctrl-device";
9 pinctrl-0 = <&test_device_default>;
10 pinctrl-names = "default";
25 drive-push-pull;
29 drive-open-drain;
33 bias-disable;
37 bias-pull-up;
41 bias-pull-down;
45 slew-rate = "max-speed-2mhz";
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| D | gd32f403z_eval.overlay | 3 * SPDX-License-Identifier: Apache-2.0
10 compatible = "vnd,pinctrl-device";
11 pinctrl-0 = <&test_device_default>;
12 pinctrl-names = "default";
32 drive-push-pull;
36 drive-open-drain;
40 bias-disable;
44 bias-pull-up;
48 bias-pull-down;
52 slew-rate = "max-speed-2mhz";
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | atmel,gmac-common.yaml | 2 # Copyright (c) 2020-2021 Gerson Fernando Budke <nandojve@gmail.com>
3 # SPDX-License-Identifier: Apache-2.0
6 - name: ethernet-controller.yaml
7 - name: pinctrl-device.yaml
13 phy-handle:
16 num-queues:
22 max-frame-size:
28 means that normally gmac will reject any frame above max-frame-size
38 max-speed:
42 This specifies maximum speed in Mbit/s supported by the device. The
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| /Zephyr-latest/subsys/bluetooth/audio/ |
| D | Kconfig.mcs | 1 # Bluetooth Audio - Media control configuration options
4 # Copyright (c) 2020-2022 Nordic Semiconductor
6 # SPDX-License-Identifier: Apache-2.0
31 int "Max length of media player name"
40 int "Max length of media player icon URL"
49 int "Max length of the title of a track"
58 int "Max length of the name of a track segment"
164 bool "Support reading Playback Speed"
167 This option enables support for reading Playback Speed.
170 bool "Support setting Playback Speed"
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| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | nucleo_g431rb.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 dma-names = "tx", "rx";
12 compatible = "test-spi-loopback-slow";
14 spi-max-frequency = <500000>;
17 compatible = "test-spi-loopback-fast";
19 spi-max-frequency = <16000000>;
33 * Reduce bus clock speed to be able to reach
34 * SPI_LOOPBACK_SLOW_FREQ = 500000 with max prescaler 256
36 apb2-prescaler = <2>;
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| D | nucleo_g474re.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 * Reduce bus clock speed to be able
11 * with max prescaler 256
13 apb2-prescaler = <2>;
19 dma-names = "tx", "rx";
21 compatible = "test-spi-loopback-slow";
23 spi-max-frequency = <500000>;
26 compatible = "test-spi-loopback-fast";
28 spi-max-frequency = <16000000>;
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| /Zephyr-latest/boards/intel/socfpga/agilex5_socdk/ |
| D | intel_socfpga_agilex5_socdk.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 compatible = "intel,socfpga-agilex5";
14 #address-cells = <1>;
15 #size-cells = <1>;
19 zephyr,shell-uart = &uart0;
28 compatible = "zephyr,sdmmc-disk";
29 disk-name = "SD";
36 current-speed = <115200>;
40 full-duplex-mode-en;
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| /Zephyr-latest/include/zephyr/drivers/i3c/ |
| D | ccc.h | 5 * SPDX-License-Identifier: Apache-2.0
91 * Set Max Write Length (Broadcast or Direct)
98 * Set Max Read Length (Broadcast or Direct)
117 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
120 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
123 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
126 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
129 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
171 /** Multi-Lane Data Transfer Control (Broadcast) */
188 /** Get Max Write Length (Direct) */
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| /Zephyr-latest/tests/drivers/spi/spi_loopback/ |
| D | overlay-mcux-flexio-spi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "150-mhz";
27 drive-strength = "r0-6";
28 slew-rate = "slow";
29 nxp,speed = "150-mhz";
37 compatible = "nxp,flexio-spi";
39 #address-cells = <1>;
40 #size-cells = <0>;
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| /Zephyr-latest/dts/bindings/can/ |
| D | can-controller.yaml | 6 bus-speed:
19 sample-point:
33 transceiver0: can-phy0 {
34 compatible = "nxp,tja1040", "can-transceiver-gpio";
35 standby-gpios = <gpioa 0 GPIO_ACTIVE_HIGH>;
36 max-bitrate = <1000000>;
37 #phy-cells = <0>;
46 child-binding:
48 Passive CAN transceiver. The child node must be named "can-transceiver".
54 can-transceiver {
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| /Zephyr-latest/samples/sensor/6dof_motion_drdy/boards/ |
| D | nrf52dk_nrf52832_spi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
8 * Get a node identifier for 6-axis IMU sensor.
12 6dof-motion-drdy0 = &icm42670p;
16 /* Example configuration of a ICM42670-P device on spi2 compatible with an Arduino SPI bus.
22 cs-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
26 spi-max-frequency = <1000000>; /* conservatively set to 1MHz */
27 int-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; /* D2 */
28 accel-hz = <100>;
29 gyro-hz = <100>;
30 accel-fs = <16>;
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| /Zephyr-latest/boards/wch/ch32v003evt/ |
| D | ch32v003evt-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h>
12 output-high;
13 drive-push-pull;
14 slew-rate = "max-speed-10mhz";
18 bias-pull-up;
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| /Zephyr-latest/dts/riscv/ |
| D | renode_riscv32_virt.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
17 clock-frequency = <0>;
22 hlic: interrupt-controller {
23 compatible = "riscv,cpu-intc";
24 #address-cells = <0>;
25 #interrupt-cells = <1>;
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| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h745.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h745", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
23 compatible = "st,stm32-nv-flash", "soc-nv-flash";
24 write-block-size = <32>;
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| /Zephyr-latest/boards/olimex/olimexino_stm32/ |
| D | olimexino_stm32.dts | 2 * Copyright (c) 2017 I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f1/stm32f103r(8-b)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "Olimex OLIMEXINO-STM32 board";
18 zephyr,shell-uart = &usart1;
25 compatible = "gpio-leds";
37 compatible = "gpio-keys";
45 transceiver0: can-phy0 {
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| /Zephyr-latest/boards/atmel/sam0/samc21n_xpro/ |
| D | samc21n_xpro.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "samc21n_xpro-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
20 zephyr,shell-uart = &sercom4;
29 pwm-led0 = &pwm_led0;
31 i2c-0 = &sercom1;
35 compatible = "gpio-leds";
43 compatible = "pwm-leds";
50 compatible = "gpio-keys";
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| /Zephyr-latest/boards/microchip/mpfs_icicle/ |
| D | mpfs_icicle_common.dtsi | 2 * Copyright (c) 2020-2021 Microchip Technology Inc
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "microchip,mpfs-icicle-kit";
14 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
23 compatible = "gpio-leds";
32 compatible = "gpio-keys";
43 current-speed = <115200>;
44 clock-frequency = <150000000>;
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| /Zephyr-latest/soc/intel/apollo_lake/doc/ |
| D | supported_features.txt | 5 etc.), Zephyr supports the following Apollo Lake-specific SoC devices:
13 HSUART High-Speed Serial Port Support
14 -------------------------------------
16 The Apollo Lake UARTs are NS16550-compatible, with "high-speed" capability.
20 in turn outputs the baud master clock. The PLL is controlled by a per-UART
21 32-bit register called ``PRV_CLOCK_PARAMS`` (aka the ``PCP``), the format of
24 +--------+---------+--------+--------+
28 +--------+---------+--------+--------+
34 results in the de-facto standard 1.8432MHz master clock and a max baud rate
43 .. code-block:: console
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| /Zephyr-latest/boards/nxp/mimxrt1170_evk/ |
| D | mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 zephyr,flash-controller = &w25q512nw;
12 zephyr,code-partition = &slot0_partition;
13 zephyr,bt-hci = &bt_hci_uart;
17 /delete-property/ magn0;
18 /delete-property/ accel0;
24 /delete-node/ is25wp128@0;
28 compatible = "nxp,imx-flexspi-nor";
31 spi-max-frequency = <133000000>;
33 jedec-id = [ef 60 20];
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| /Zephyr-latest/boards/shields/x_nucleo_wb05kn1/ |
| D | x_nucleo_wb05kn1_spi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,bt-hci = &hci_spi;
14 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
17 compatible = "st,hci-spi-v2";
19 reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
20 irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */
21 spi-cpol; /* CPOL=1 */
22 spi-cpha; /* CPHA=1 */
23 spi-hold-cs;
24 spi-max-frequency = <DT_FREQ_M(8)>; /* the maximum supported SPI speed */
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| /Zephyr-latest/boards/m5stack/m5stack_core2/ |
| D | m5stack_core2_procpu.dts | 4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "m5stack_core2-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/display/ili9xxx.h>
13 #include <zephyr/dt-bindings/regulator/axp192.h>
21 pwr-led = &pwr_led;
22 uart-0 = &uart0;
23 i2c-0 = &i2c0;
33 zephyr,shell-uart = &uart0;
36 zephyr,code-partition = &slot0_partition;
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