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/Zephyr-latest/dts/bindings/pinctrl/
Dwch,afio.yaml2 # SPDX-License-Identifier: Apache-2.0
13 "#address-cells":
16 "#size-cells":
20 child-binding:
23 child-binding:
28 - name: pincfg-node.yaml
29 property-allowlist:
30 - bias-high-impedance
31 - bias-pull-up
32 - bias-pull-down
[all …]
Dgd,gd32-pinctrl-af.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
35 /* group 2 */
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
[all …]
Dgd,gd32-pinctrl-afio.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
35 /* group 2 */
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
[all …]
Dst,stm32f1-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
27 - "disable"
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Dnxp,mcux-rt-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
22 slow slew rate, and 100 MHZ speed.
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
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/Zephyr-latest/tests/drivers/pinctrl/gd32/boards/
Dgd32f450i_eval.overlay3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "vnd,pinctrl-device";
9 pinctrl-0 = <&test_device_default>;
10 pinctrl-names = "default";
24 pinmux = <GD32_PINMUX_AF('C', 2, AF2)>;
25 drive-push-pull;
29 drive-open-drain;
33 bias-disable;
37 bias-pull-up;
41 bias-pull-down;
[all …]
Dgd32f403z_eval.overlay3 * SPDX-License-Identifier: Apache-2.0
10 compatible = "vnd,pinctrl-device";
11 pinctrl-0 = <&test_device_default>;
12 pinctrl-names = "default";
24 <GD32_PINMUX_AFIO('C', 2, GPIO_IN, NORMP)>;
32 drive-push-pull;
36 drive-open-drain;
40 bias-disable;
44 bias-pull-up;
48 bias-pull-down;
[all …]
/Zephyr-latest/tests/drivers/spi/spi_loopback/
Doverlay-mcux-flexio-spi.overlay4 * SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "150-mhz";
27 drive-strength = "r0-6";
28 slew-rate = "slow";
29 nxp,speed = "150-mhz";
37 compatible = "nxp,flexio-spi";
39 #address-cells = <1>;
40 #size-cells = <0>;
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/Zephyr-latest/soc/espressif/common/
DKconfig.esptool2 # SPDX-License-Identifier: Apache-2.0
21 …2. If the flash chip is a Quad one, even if "OPI" is selected in `ESPTOOLPY_FLASHMODE`, our code w…
75 # The 1st and 2nd bootloader doesn't support opi mode,
77 # fasted (see ESPTOOL-274), using dout instead. In ROM the flash mode
82 prompt "Flash SPI speed"
88 bool "120 MHz"
92 - Flash 120 MHz SDR mode is stable.
93 - Flash 120 MHz DDR mode is an experimental feature, it works when
102 bool "80 MHz"
104 bool "60 MHz"
[all …]
/Zephyr-latest/include/zephyr/sd/
Dsd_spec.h2 * Copyright 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
31 SD_ALL_SEND_CID = 2,
69 * to inform the SD card the next command is an application-specific one.
87 /* Bits 0-2 reserved */
99 /* Bits 17-18 reserved */
141 SDMMC_R1_IDENTIFY = 2U,
160 SD_SPI_R1ILLEGAL_CMD_ERR = BIT(2),
184 #define SD_SPI_CMD_BODY_SIZE (SD_SPI_CMD_SIZE - 1)
186 #define SD_SPI_CRC16_SIZE 2
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/Zephyr-latest/boards/96boards/argonkey/
D96b_argonkey.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f412c(e-g)ux-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &usart1;
24 compatible = "gpio-leds";
30 gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
36 compatible = "gpio-keys";
39 gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
57 clock-frequency = <DT_FREQ_M(16)>;
[all …]
/Zephyr-latest/boards/olimex/olimexino_stm32/
Dolimexino_stm32.dts2 * Copyright (c) 2017 I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f1/stm32f103r(8-b)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "Olimex OLIMEXINO-STM32 board";
18 zephyr,shell-uart = &usart1;
25 compatible = "gpio-leds";
37 compatible = "gpio-keys";
45 transceiver0: can-phy0 {
[all …]
/Zephyr-latest/include/zephyr/drivers/i3c/
Dccc.h5 * SPDX-License-Identifier: Apache-2.0
68 * Enter Activity State 2
72 #define I3C_CCC_ENTAS2(broadcast) I3C_CCC_ENTAS(2, broadcast)
91 * Set Max Write Length (Broadcast or Direct)
98 * Set Max Read Length (Broadcast or Direct)
117 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
120 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
123 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
126 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
129 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
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/Zephyr-latest/boards/96boards/avenger96/doc/
Dindex.rst10 multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
11 core. Zephyr OS is ported to run on the Cortex®-M4 core.
13 - Board features:
15 - PMIC: STPMIC1A
16 - RAM: 1024 Mbyte @ 533MHz
17 - Storage:
19 - eMMC: v4.51: 8 Gbyte
20 - QSPI: 2Mbyte
21 - EEPROM: 128 byte
22 - microSD Socket: UHS-1 v3.01
[all …]
/Zephyr-latest/boards/st/stm32h7b3i_dk/
Dstm32h7b3i_dk.dts2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 compatible = "st,stm32h7b3i-dk";
20 zephyr,shell-uart = &usart1;
29 compatible = "gpio-leds";
35 gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/boards/st/stm32h745i_disco/
Dstm32h745i_disco_stm32h745xx_m7.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
13 model = "STMicroelectronics STM32H745I-DISCO board";
14 compatible = "st,stm32h745i-disco";
19 zephyr,shell-uart = &usart3;
23 zephyr,flash-controller = &mt25ql512ab1;
28 compatible = "pwm-leds";
32 label = "User LD8 - PWM11";
36 /* RM0455 - 23.6 External device address mapping */
38 compatible = "zephyr,memory-region", "mmio-sram";
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_led_esp32.c5 * SPDX-License-Identifier: Apache-2.0
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
30 #define SCLK_CLK_FREQ MHZ(60)
32 #define SCLK_CLK_FREQ MHZ(80)
64 (struct pwm_ledc_esp32_config *) dev->config; in get_channel_config()
66 for (uint8_t i = 0; i < config->channel_len; i++) { in get_channel_config()
67 if (config->channel_config[i].idx == channel_id) { in get_channel_config()
68 return &config->channel_config[i]; in get_channel_config()
76 struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data; in pwm_led_esp32_low_speed_update()
79 ledc_hal_ls_channel_update(&data->hal, channel); in pwm_led_esp32_low_speed_update()
[all …]
/Zephyr-latest/boards/fanke/fk7b0m1_vbt6/
Dfk7b0m1_vbt6.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h7b0vbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "FANKE FK7B0M1-VBT6 board";
15 compatible = "fanke,fk7b0m1-vbt6";
19 zephyr,shell-uart = &usart1;
25 compatible = "gpio-leds";
33 compatible = "gpio-keys";
[all …]
/Zephyr-latest/boards/seagate/legend/
Dlegend.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f0/stm32f070cbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/led/led.h>
11 #include <zephyr/dt-bindings/led/seagate_legend_b1414.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 zephyr,shell-uart = &usart1;
24 led-strip = &led_strip_spi;
27 board_id: brd-id {
28 compatible = "gpio-keys";
[all …]
/Zephyr-latest/boards/arduino/portenta_h7/
Darduino_portenta_h7-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "gpio-leds";
24 compatible = "usb-ulpi-phy";
25 reset-gpios = < &gpioj 4 GPIO_ACTIVE_LOW >;
26 #phy-cells = <0>;
43 hpre = < 2 >;
44 d1ppre = < 2 >;
45 d2ppre1 = < 2 >;
46 d2ppre2 = < 2 >;
47 d3ppre = < 2 >;
[all …]
/Zephyr-latest/boards/st/stm32f412g_disco/
Dstm32f412g_disco.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f412z(e-g)tx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32F412G-DISCO board";
15 compatible = "st,stm32f412g-disco";
19 zephyr,shell-uart = &usart2;
25 compatible = "gpio-leds";
35 gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
45 compatible = "gpio-keys";
[all …]
/Zephyr-latest/boards/st/nucleo_h723zg/doc/
Dindex.rst6 The STM32 Nucleo-144 board provides an affordable and flexible way for users
15 The STM32 Nucleo-144 board does not require any separate probe as it integrates
16 the ST-LINK V3 debugger/programmer.
18 The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
23 - STM32 microcontroller in LQFP144 package
24 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
25 - USB OTG or full-speed device (depending on STM32 support)
26 - 3 user LEDs
27 - 2 user and reset push-buttons
28 - 32.768 kHz crystal oscillator
[all …]
/Zephyr-latest/boards/weact/mini_stm32h743/doc/
Dindex.rst13 - STM32 microcontroller in LQFP100 package
14 - USB OTG or full-speed device
15 - 1 user LED
16 - User, boot, and reset push-buttons
17 - 32.768 kHz and 25MHz HSE crystal oscillators
18 - External NOR Flash memories: 64-Mbit Quad-SPI and 64-Mbit SPI
19 - Board connectors:
20 - Camera (8 bit) connector
21 - ST7735 TFT-LCD 160 x 80 pixels (RGB565 3-SPI)
22 - microSD |trade| card
[all …]
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.h3 * SPDX-License-Identifier: Apache-2.0
15 #define CDNS_HRS09_EXT_RD_MODE(x) ((x) << 2)
26 /* SRS09 - Present State Register */
27 #define CDNS_SRS09_STAT_DAT_BUSY BIT(2)
30 /* SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up) */
33 #define HS_EN BIT(2)
53 #define CDNS_SRS11_SDCE BIT(2)
64 * • 1111b - Reserved
65 * • 1110b - t_sdmclk*2(27+2)
66 * • 1101b - t_sdmclk*2(26+2)
[all …]
/Zephyr-latest/boards/weact/stm32f405_core/doc/
Dindex.rst6 The WeAct STM32F405 Core Board is an extremely low cost and bare-bones
8 This is the 64-pin variant of the STM32F405x series,
18 - STM32F405RG in QFPN64 package
19 - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time
20 accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory
21 - 168 MHz max CPU frequency
22 - VDD from 1.7 V to 3.6 V
23 - 1 MB Flash
24 - 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory)
25 - GPIO with external interrupt capability
[all …]

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